Merged write driver based on local source line MRAM architecture
The present disclosure relates to a structure which includes a merged write driver circuit with a first device next to a first memory array and a second device next to a second memory array, and the merged write driver circuit being configured to share a write driver line between the first device and the second device.
1. A structure comprising:
a merged write driver circuit with a first device next to a first memory array and a second device next to a second memory array, wherein the merged write driver circuit is configured to share a write driver line between the first device and the second device, wherein the first device and the second device are each a NMOS transistor;
a plurality of reference bit lines connected to the merged write driver circuit through a plurality of pull ups;
a first set of transistors with a drain connected to the plurality of reference bit lines and a source connected to a global source line;
a second set of transistors with a drain connected to a word line and a source connected to a common source line; and
an unused global mux output of the first set of transistors which is connected to a pull down leg to complete a current loop for performing a write operation of data.
2. The structure of claim 1 , wherein the first device comprises a source which is connected to the write driver line.
3. The structure of claim 2 , wherein the second device comprises a source which is connected to the write driver line.
4. The structure of claim 1 , wherein the first memory array and the second memory array are part of a magnetoresistive random access memory (MRAM).
5. The structure of claim 1 , wherein the write driver line shared between the first device and the second device provides a current driving capability using a same predetermined area.
6. The structure of claim 1 , wherein the write driver line being shared between the first device and the second device provides an area efficiency with a same predetermined current driving capability.
7. The structure of claim 1 , wherein the merged write driver circuit and the write driver line being shared between the first device and the second device provide a write operation of data.
8. The structure of claim 7 , wherein the write operation of the data comprises a down write operation of the data.
9. The structure of claim 7 , wherein the write operation of the data comprises an up write operation of the data.
10. A circuit, comprising:
a plurality of bit lines;
a plurality of reference bit lines;
a merged write driver circuit connected to a shared write driver line and which is connected to the plurality of reference bit lines through a plurality of pull ups;
a first set of transistors with a drain connected to the plurality of reference bit lines and a source connected to a global source line;
a second set of transistors with a drain connected to a word line and a source connected to a common source line; and
an unused global mux output in the first set of transistors which is connected to a pull down leg to complete a current loop for performing a write operation of data.
11. The circuit of claim 10 , wherein the unused global mux output is connected to the pull down leg to enable a pull down to ground.
12. The circuit of claim 10 , wherein the first set of transistors comprises NMOS transistors.
13. The circuit of claim 12 , wherein the second set of transistors comprises NMOS transistors.
14. The circuit of claim 13 , wherein the plurality of reference bit lines comprises a reference data bit line receiving the data.
15. The circuit of claim 14 , wherein the write operation of the data is a down write operation of the data.
16. A method, comprising:
sharing a write driver line between a first device comprising a first NMOS transistor next to a first memory array and a second device comprising a second NMOS transistor next to a second memory array; and
performing a write operation of data with the shared write driver line being connected to a merged write driver circuit which includes the first device and the second device,
wherein
a plurality of reference bit lines are connected to the merged write driver circuit through a plurality of pull ups;
a first set of transistors includes a drain connected to the plurality of reference bit lines and a source connected to a global source line;
a second set of transistors includes a drain connected to a word line and a source connected to a common source line; and
an unused global mux output of the first set of transistors is connected to a pull down leg to complete a current loop for performing a write operation of data.
17. The method of claim 16 , wherein the performing the write operation of the data further comprises performing a down write operation of the data.
18. The method of claim 16 , wherein the performing the write operation of the data further comprises performing an up write operation of the data.
19. The method of claim 16 , wherein the first memory array and the second memory array are part of a magnetoresistive random access memory (MRAM).