Semiconductor layer between source/drain regions and gate spacers
A semiconductor device is described that includes a first semiconductor layer conformally disposed on at least a portion of a source region and a second semiconductor layer conformally disposed on at least a portion of a drain region between the source/drain regions and corresponding gate spacers. The semiconductor layer can prevent diffusion and/or segregation of dopants from the source and drain regions into the gate spacers of the gate stack. Maintaining the intended location of dopant atoms in the source region and drain region improves the electrical characteristics of the semiconductor device including the external resistance (“R ext ”) of the semiconductor device.
1. An integrated circuit device comprising:
a semiconductor body comprising a first semiconductor material;
a source region on a first side of the semiconductor body, the source region comprising a second semiconductor material compositionally different from the first semiconductor material;
a drain region on a second side of the semiconductor body opposite the first side, the source region comprising the second semiconductor material;
a gate structure including a first gate spacer at least partially over the source region and a second gate spacer at least partially over the drain region;
a first semiconductor layer between the source region and the first gate spacer comprising a third semiconductor material compositionally different from the first semiconductor material and the second semiconductor material; and
a second semiconductor layer between the drain region and the second gate spacer comprising the third semiconductor material.
2. The integrated circuit device of claim 1 , wherein:
the semiconductor body comprises silicon and germanium;
the first semiconductor layer comprises silicon; and
the second semiconductor layer comprises silicon.
3. The integrated circuit device of claim 1 , wherein:
the semiconductor body comprises indium, gallium, and arsenic;
the first semiconductor layer comprises indium and phosphorous; and
the second semiconductor layer comprises indium and phosphorous.
4. The integrated circuit device of claim 1 , wherein:
the semiconductor body comprises indium, gallium, and arsenic;
the first semiconductor layer comprises indium, gallium, aluminum, and nitrogen; and
the second semiconductor layer comprises indium, gallium, aluminum, and nitrogen.
5. The integrated circuit device of claim 1 , wherein:
the semiconductor body comprises gallium and arsenic;
the first semiconductor layer comprises indium and phosphorous; and
the second semiconductor layer comprises indium and phosphorous.
6. The integrated circuit device of claim 1 , wherein:
the semiconductor body comprises gallium and arsenic;
the first semiconductor layer comprises indium, gallium, aluminum, and nitrogen; and
the second semiconductor layer comprises indium, gallium, aluminum, and nitrogen.
7. The integrated circuit device of claim 1 , wherein:
the source region and the drain region comprise a dopant material; and
the first gate spacer and the second gate spacer are depleted of the dopant material because the first semiconductor layer isolates the source region from the first gate spacer, and the second semiconductor layer isolates the drain region from the second gate spacer.
8. The integrated circuit device of claim 1 , wherein the first semiconductor layer is a single crystal, and wherein crystallographic planes of the single crystal first semiconductor layer have a one to one epitaxial correspondence with corresponding planes of a single crystal source region.
9. The integrated circuit device of claim 1 , wherein the second semiconductor layer is a single crystal, and wherein crystallographic planes of the single crystal second semiconductor layer have a one to one epitaxial correspondence with corresponding planes of a single crystal drain region.
10. The integrated circuit device of claim 1 , wherein the first semiconductor layer and the second semiconductor layer are conformal to a top surface and at least portions of opposing side surfaces of the source region and the drain region, respectively.
11. The integrated circuit device of claim 10 , wherein the conformal first and second semiconductor layers separate the source region and the drain region from the first gate spacer and the second gate spacer, respectively.
12. The integrated circuit device of claim 1 , wherein the first semiconductor layer and the second semiconductor layer are from 0.2 nm to 4 nm thick.
13. The integrated circuit device of claim 1 , wherein the first semiconductor layer and the second semiconductor layer are from 1 nm to 3 nm thick.
14. The integrated circuit device of claim 1 , wherein the first semiconductor layer and the second semiconductor layer have a width within 1 nm of the first gate spacer and the second gate spacer, respectively.
15. The integrated circuit device of claim 1 , wherein the semiconductor body is a fin structure and the gate structure is on a top and opposing sides of the fin so as to provide a finFET structure.
16. The integrated circuit device of claim 1 , wherein the semiconductor body includes one or more nanowires and the gate structure is around the one or more nanowires so as to provide a gate-all-around structure.
17. A method for fabricating a semiconductor device, the method comprising:
forming a semiconductor body comprising a first semiconductor material;
forming a gate structure on a top surface and opposing sidewalls of the semiconductor body, thereby defining a non-planar channel region in the semiconductor body, the gate structure including a gate dielectric structure on the top and the opposing sidewalls of the semiconductor body, a gate electrode structure on the gate dielectric structure, and first and second gate spacers on opposing sides of the gate dielectric structure;
forming a source region and a drain region adjacent to the semiconductor body, the source region and the drain region on opposite sides of the semiconductor body and comprising a second semiconductor material compositionally different from the first semiconductor material; and
forming a first semiconductor layer on the source region between the source region and the first gate spacer and a second semiconductor layer on the drain region between the drain region and the second gate spacer, the first and second semiconductor layers comprising a third semiconductor material compositionally different from the first semiconductor material and the second semiconductor material.
18. The method of claim 17 , wherein the first semiconductor layer and the second semiconductor layer are epitaxially formed with the source region and the drain region, respectively.
19. The method of claim 17 , wherein the first semiconductor layer and the second semiconductor layer are conformally disposed over the source region and the drain region from a top surface of a corresponding one of the source region and the drain region to a bottom interface with a shallow trench isolation layer.
20. The method of claim 17 , wherein the first semiconductor layer and the second semiconductor layer are from 0.2 nm to 4 nm thick.