Method for fabricating semiconductor device
A method for fabricating semiconductor device includes the steps of first forming a metal gate on a substrate and a spacer around the metal gate, in which the metal gate comprises a high-k dielectric layer, a work function metal layer, and a low-resistance metal layer. Next, part of the high-k dielectric layer is removed to form an air gap between the work function metal layer and the spacer.
1. A method for fabricating semiconductor device, comprising:
forming a metal gate on a substrate and a spacer around the metal gate, wherein the metal gate comprises a high-k dielectric layer, a work function metal layer, and a metal layer; and
removing part of the high-k dielectric layer to form an air gap between the work function metal layer and the spacer and contacting the high-k dielectric layer directly.
2. The method of claim 1 , further comprising:
forming a gate structure on the substrate;
forming the spacer around the gate structure;
forming an interlayer dielectric (ILD) layer around the spacer; and
performing a replacement metal gate (RMG) process to transform the gate structure into the metal gate.
3. The method of claim 2 , further comprising:
performing a first etching process to remove part of the work function metal layer;
performing a second etching process to remove part of the metal layer;
performing a third etching process to remove part of the work function metal layer; and
performing a fourth etching process to remove part of the high-k dielectric layer.
4. The method of claim 3 , further comprising performing the first etching process so that a top surface of the metal layer is higher than a top surface of the work function metal layer.
5. The method of claim 3 , further comprising performing the second etching process so that a top surface of the work function metal layer is higher than a top surface of the metal layer.
6. The method of claim 3 , further comprising performing the third etching process so that a top surface of the metal layer is higher than a top surface of the work function metal layer.
7. The method of claim 3 , further comprising performing the fourth etching process to remove part of the high-k dielectric layer so that the top surfaces of the work function metal layer and the high-k dielectric layer are coplanar.
8. The method of claim 3 , further comprising performing a fifth etching process to remove part of the high-k dielectric layer so that a top surface of the work function metal layer is higher than a top surface of the high-k dielectric layer.
9. The method of claim 1 , further comprising forming a hard mask on the work function metal layer and the metal layer.
10. The method of claim 9 , wherein the air gap is between the hard mask and the high-k dielectric layer.