Envelope tracking bias circuit
An envelope tracking (ET) bias circuit includes an envelope tracking (ET) bias circuit includes an envelope detection circuit, an envelope amplifier circuit, and an envelope output circuit. The envelope detection circuit is configured to detect an envelope of an input signal, and output an envelope signal based on the detected envelope of the input signal. The envelope amplifier circuit is configured to differentially amplify the envelope signal in response to a first control signal and cancel a direct current (DC) offset of the envelope signal to output an amplified signal from which the DC offset is canceled. The envelope output circuit is configured to generate an ET bias current by selecting either one of a negative signal of the amplified signal and a positive signal of the amplified signal in response to a second control signal.
1. An envelope tracking (ET) bias circuit, comprising:
an envelope detection circuit configured to detect an envelope of an input signal, and output an envelope signal based on the detected envelope of the input signal;
an envelope amplifier circuit configured to differentially amplify the envelope signal in response to a first control signal and cancel a direct current (DC) offset of the envelope signal to output an amplified signal from which the DC offset is canceled; and
an envelope output circuit configured to generate an ET bias current by selecting either one of a negative signal of the amplified signal and a positive signal of the amplified signal in response to a second control signal,
wherein the envelope output circuit comprise an ET sourcing/sinking circuit configured to generate the ET bias current based on the selected one of the first signal and the second signal.
2. The envelope tracking bias circuit of claim 1 , wherein the envelope signal output by the envelope detection circuit is a differential envelope signal, and
the envelope amplifier circuit comprises:
an amplifier configured to differentially amplify the differential envelope signal to output a differential amplified signal; and
a DC offset cancelling circuit configured to provide the amplified signal from the amplifier to an input terminal of the amplifier to cancel the DC offset from the amplified signal output from the amplifier.
3. An envelope tracking (ET) bias circuit, comprising:
an envelope detection circuit configured to detect an envelope of an input signal, and output an envelope signal based on the detected envelope of the input signal;
an envelope amplifier circuit configured to differentially amplify the envelope signal in response to a first control signal and cancel a direct current (DC) offset of the envelope signal to output an amplified signal from which the DC offset is canceled; and
an envelope output circuit configured to generate an ET bias current by selecting either one of a negative signal of the amplified signal and a positive signal of the amplified signal in response to a second control signal,
wherein the envelope signal of the envelope detection circuit is a single envelope signal, and
the envelope amplifier circuit comprises:
a single/differential circuit configured to convert the single envelope signal into a differential envelope signal;
an amplifier configured to differentially amplify the differential envelope signal from the single/differential circuit to output a differential amplified signal; and
a DC offset cancelling circuit configured to provide the amplified signal from the amplifier to an input terminal of the amplifier to cancel the DC offset from the amplified signal output from the amplifier.
4. The envelope tracking bias circuit of claim 2 , wherein the amplifier comprises a first amplifier having a non-inverting input terminal configured to receive a first signal of the differential envelope signal through a first resistor, and an inverting input terminal configured to receive a second signal of the differential envelope signal through a second resistor,
the first amplifier is configured to receive a second signal of a DC offset cancel signal from the DC offset cancelling circuit through a third resistor and the non-inverting input terminal, and receive a first signal of the DC offset cancel signal through a fourth resistor and the inverting input terminal, and
the first amplifier comprises:
a fifth resistor connected between the non-inverting input terminal and a second output terminal;
a sixth resistor connected between the inverting input terminal and a first output terminal;
a first capacitor connected between the non-inverting input terminal and the second output terminal; and
a second capacitor connected between the inverting input terminal and the first output terminal.
5. The envelope tracking bias circuit of claim 3 , wherein the amplifier comprises a first amplifier having a non-inverting input terminal receiving a first signal of the differential envelope signal through a first resistor, and an inverting input terminal configured to receive a second signal of the differential envelope signal through a second resistor,
the first amplifier is configured to receive a second signal of a DC offset cancel signal from the DC offset cancelling circuit through a third resistor and the non-inverting input terminal, and receive a first signal of the DC offset cancel signal through a fourth resistor and the inverting input terminal, and
the first amplifier comprises:
a fifth resistor connected between the non-inverting input terminal and a second output terminal;
a sixth resistor connected between the inverting input terminal and a first output terminal;
a first capacitor connected between the non-inverting input terminal and the second output terminal; and
a second capacitor connected between the inverting input terminal and the first output terminal.
6. The envelope tracking bias circuit of claim 2 , wherein the DC offset cancelling circuit comprises a second amplifier having a non-inverting input terminal connected to a first output terminal of the amplifier through first and second resistors, and an inverting input terminal connected to a second output terminal of the amplifier through third and fourth resistors,
the second amplifier is configured to provide a DC offset bias voltage through fifth and sixth resistors connected between a connection node of the first and second resistors and a connection node of the third and fourth resistors, and
the second amplifier comprises:
a first capacitor connected between the non-inverting input terminal and a second output terminal of the DC offset cancelling circuit; and
a second capacitor connected between the inverting input terminal and a first output terminal of the DC offset cancelling circuit.
7. The envelope tracking bias circuit of claim 3 , wherein the DC offset cancelling circuit comprises a second amplifier having a non-inverting input terminal connected to a first output terminal of the amplifier through first and second resistors, and an inverting input terminal connected to a second output terminal of the amplifier through third and fourth resistors,
the second amplifier is configured to provide a DC offset bias voltage through fifth and sixth resistors connected between a connection node of the first and second resistors and a connection node of the third and fourth resistors, and
the second amplifier comprises:
a first capacitor connected between the non-inverting input terminal and a second output terminal of the DC offset cancelling circuit; and
a second capacitor connected between the inverting input terminal and a first output terminal of the DC offset cancelling circuit.
8. The envelope tracking bias circuit of claim 2 , wherein the envelope output circuit comprises:
a selection circuit configured to select either one of a first signal and a second signal of the amplified signal in response to the second control signal.
9. The envelope tracking bias circuit of claim 3 , wherein the envelope output circuit comprises:
a selection circuit configured to select either one of a first signal and a second signal of the amplified signal in response to the second control signal; and
an ET sourcing/sinking circuit configured to generate the ET bias current based on the selected one of the first signal and the second signal.
10. The envelope tracking bias circuit of claim 8 , wherein the ET sourcing/sinking circuit comprises:
an ET current generation circuit configured to convert a voltage selected by the selection circuit into the ET bias current and adjust the ET bias current in response to the second control signal; and
a DC bias cancel circuit configured to convert the DC offset bias voltage into the ET bias current and cancel the direct current from the ET bias current.
11. The envelope tracking bias circuit of claim 9 , wherein the ET sourcing/sinking circuit comprises:
an ET current generation circuit configured to convert a voltage selected by the selection circuit into the ET bias current and adjust the ET bias current in response to the second control signal; and
a DC bias cancel circuit configured to convert the DC offset bias voltage into the ET bias current and cancel the direct current from the ET bias current.
12. An envelope tracking (ET) bias circuit, comprising:
an envelope detection circuit configured to detect an envelope from an input signal, and output an envelope signal based on the detected envelope;
an envelope amplifier circuit configured to differentially amplify the envelope signal in response to a first control signal, and cancel a direct current (DC) offset of the envelope signal to output an amplified signal from which the DC offset is canceled;
an envelope output circuit configured to generate an ET bias current by selecting either one of a negative signal of the amplified signal and a positive signal of the amplified signal in response to the second control signal; and
a control circuit configured to generate the first control signal and the second control signal to control the envelope amplifier circuit and the envelope output circuit based on a characteristic parameter factor of a power amplifier,
wherein the envelope output circuit comprise an ET sourcing/sinking circuit configured to generate the ET bias current based on the selected one of the negative signal and the positive signal.
13. The envelope tracking bias circuit of claim 12 , wherein the envelope signal of the envelope detection circuit is a differential envelope signal, and
the envelope amplifier circuit comprises:
an amplifier configured to differentially amplify the differential envelope signal to output a differential amplified signal; and
a DC offset cancelling circuit configured to provide the amplified signal from the amplifier to an input terminal of the amplifier to cancel the DC offset from the amplified signal output from the amplifier.
14. The envelope tracking bias circuit of claim 12 , wherein the envelope signal of the envelope detection circuit is a single envelope signal, and
the envelope amplifier circuit comprises:
a single/differential circuit configured to convert the single envelope signal into a differential envelope signal;
an amplifier configured to differentially amplify the differential envelope signal from the single/differential circuit to output a differential amplified signal; and
a DC offset cancelling circuit configured to provide the amplified signal from the amplifier to an input terminal of the amplifier to cancel the DC offset from the amplified signal output from the amplifier.
15. The envelope tracking bias circuit of claim 13 , wherein the amplifier comprises a first amplifier having a non-inverting input terminal configured to receive a first signal of the differential envelope signal through a first resistor, and an inverting input terminal configured to receive a second signal of the differential envelope signal through a second resistor,
the first amplifier is configured to receive a second signal of a DC offset cancel signal from the DC offset cancelling circuit through a third resistor and the non-inverting input terminal, and receive a first signal of the DC offset cancel signal through a fourth resistor and the inverting input terminal, and
the first amplifier comprises:
a fifth resistor connected between the non-inverting input terminal and a second output terminal;
a sixth resistor connected between the inverting input terminal and a first output terminal;
a first capacitor connected between the non-inverting input terminal and the second output terminal; and
a second capacitor connected between the inverting input terminal and the first output terminal.
16. The envelope tracking bias circuit of claim 14 , wherein the amplifier comprises a first amplifier having a non-inverting input terminal configured to receive a first signal of the differential envelope signal through a first resistor, and an inverting input terminal configured to receive a second signal of the differential envelope signal through a second resistor,
the first amplifier is configured to receive a second signal of a DC offset cancel signal from the DC offset cancelling circuit through a third resistor and the non-inverting input terminal, and receive a first signal of the DC offset cancel signal through a fourth resistor and the inverting input terminal, and
the first amplifier comprises:
a fifth resistor connected between the non-inverting input terminal and a second output terminal;
a sixth resistor connected between the inverting input terminal and a first output terminal;
a first capacitor connected between the non-inverting input terminal and the second output terminal; and
a second capacitor connected between the inverting input terminal and the first output terminal.
17. The envelope tracking bias circuit of claim 13 , wherein the DC offset cancelling circuit comprises a second amplifier having a non-inverting input terminal connected to a first output terminal of the amplifier through first and second resistors, and an inverting input terminal connected to a second output terminal of the amplifier through third and fourth resistors,
the second amplifier is configured to provide a DC offset bias voltage through fifth and sixth resistors connected between a connection node of the first and second resistors and a connection node of the third and fourth resistors, and
the second amplifier comprises:
a first capacitor connected between the non-inverting input terminal and a second output terminal of the DC offset cancelling circuit; and
a second capacitor connected between the inverting input terminal and a first output terminal of the DC offset cancelling circuit.
18. The envelope tracking bias circuit of claim 14 , wherein the DC offset cancelling circuit comprises a second amplifier having a non-inverting input terminal connected to a first output terminal of the amplifier through first and second resistors, and an inverting input terminal connected to a second output terminal of the amplifier through third and fourth resistors,
the second amplifier is configured to provide a DC offset bias voltage through fifth and sixth resistors connected between a connection node of the first and second resistors and a connection node of the third and fourth resistors, and
the second amplifier comprises:
a first capacitor connected between the non-inverting input terminal and a second output terminal of the DC offset cancelling circuit; and
a second capacitor connected between the inverting input terminal and a first output terminal of the DC offset cancelling circuit.
19. The envelope tracking bias circuit of claim 13 , wherein the envelope output circuit comprises:
a selection circuit configured to select either one of a first signal and a second signal of the amplified signal in response to the second control signal.
20. The envelope tracking bias circuit of claim 14 , wherein the envelope output circuit comprises:
a selection circuit configured to select either one of a first signal and a second signal of the amplified signal in response to the second control signal.
21. The envelope tracking bias circuit of claim 19 , wherein the ET sourcing/sinking circuit comprises:
an ET current generation circuit configured to convert a voltage selected by the selection circuit into the ET bias current and adjust the ET bias current in response to the second control signal; and
a DC bias cancel circuit configured to convert the DC offset bias voltage into the ET bias current and cancel the direct current from the ET bias current.
22. The envelope tracking bias circuit of claim 20 , wherein the ET sourcing/sinking circuit comprises:
an ET current generation circuit configured to convert a voltage selected by the selection circuit into the ET bias current and adjust the ET bias current in response to the second control signal; and
a DC bias cancel circuit configured to convert the DC offset bias voltage into the ET bias current and cancel the direct current from the ET bias current.