IP Library Granted Patent US 10,719,437
Granted Patent B2
US 10,719,437 · App. 15/984,944 · Granted Jul 21, 2020

Memory system and method for controlling nonvolatile memory

Inventors: Hideki Yoshida (Yokohama Kanagawa, JP); Shinichi Kanno (Tokyo, JP)
Assignee: Toshiba Memory Corporation
G06F12/0246G06F3/06G06F3/064G06F12/0253G06F12/06G06F12/10G06F2212/1016G06F2212/152G06F2212/2022G06F2212/7201G06F2212/7202G06F2212/7205G06F2212/7208
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Quick Facts
Patent No.
US 10,719,437
App. No.
15/984,944
Granted
Jul 21, 2020
Kind
B2
Abstract

According to one embodiment, a memory system includes a nonvolatile memory including plural blocks each including plural pages, and a controller. When receiving a write request designating a first logical address and a first block number from the host, the controller determines a first location in a first block having the first block number to which data from the host should be written, and writes the data from the host to the first location in the first block. The controller notifies the host of either an in-block physical address indicative of the first location, or a group of the first logical address, the first block number and the first in-block physical address.

Claims (48)

1. A memory system connectable to a host, comprising:

a nonvolatile memory including plural blocks each including plural pages; and

a controller electrically connected to the nonvolatile memory and configured to control the nonvolatile memory, wherein

the controller is configured:

when receiving a write request designating a first logical address and a first block number from the host, to determine a first location in a first block having the first block number to which data from the host is to be written, to write the data from the host to the first location in the first block, and to notify the host of either a first in-block physical address indicative of the first location, or a group of the first logical address, the first block number, and the first in-block physical address; and

when receiving from the host a control command designating a copy source block number and a copy destination block number for garbage collection of the nonvolatile memory, to select a second block having the copy source block number and a third block having the copy destination block number, from the plural blocks, to determine a copy destination location in the third block to which valid data stored in the second block is to be written, to copy the valid data to the copy destination location in the third block, and to notify the host of a logical address of the valid data, the copy destination block number, and a second in-block physical address indicative of the copy destination location.

2. The memory system of claim 1 , wherein

the controller is configured, when the controller receives a read request designating the first block number and the first in-block physical address from the host, to read data from the first location in the first block, based on the first block number and the first in-block physical address.

3. The memory system of claim 1 , wherein

the first in-block physical address is represented by a first in-block offset indicative of an offset from a leading part of the first block to the first location by a multiple of grain having a size different from a page size, and

the second in-block physical address is represented by a second in-block offset indicative of an offset from a leading part of the third block to the copy destination location by a multiple of the grain.

4. The memory system of claim 1 , wherein

the controller is configured:

when receiving the write request from the host, to write the first logical address to the first block together with the data from the host; and

when receiving the control command from the host, to copy both of the valid data and a logical address of the valid data which are stored in the second block, to the third block.

5. The memory system of claim 1 , wherein

the controller is configure:

to manage free blocks in the plural blocks; and

when receiving a block allocate request from the host, to allocate one free block of the free blocks to the host, and to notify the host of a block number of the allocated block, and

the first block number is indicative of the block number of the free block allocated to the host by the controller.

6. The memory system of claim 1 , wherein

the controller is configured:

when receiving a first command requesting a maximum block number from the host, to notify the host of the maximum block number indicative of the number of the plural blocks; and

when receiving a second command requesting the block size from the host, to notify the host of a block size of each of the plural blocks.

7. The memory system of claim 6 , wherein

the controller is configured, when a block number is included in the second command, to notify the host of a block size of a block having the block number included in the second command.

8. A memory system connectable to a host, comprising:

a nonvolatile memory including plural blocks each including plural pages; and

a controller electrically connected to the nonvolatile memory and configured to control the nonvolatile memory, wherein

the controller is configured:

when receiving a first command requesting a maximum block number from the host, to notify the host of the maximum block number indicative of the number of the plural blocks;

when receiving a second command requesting a block size from the host, to notify the host of a block size of each of the plural blocks;

when receiving a write request designating a first logical address and a first block number from the host, to determine a first location in a first block having the first block number to which data from the host is to be written, to write the data from the host to the first location in the first block, and to notify the host of either a first in-block physical address indicative of the first location, or a group of the first logical address, the first block number, and the first in-block physical address; and

when receiving from the host a control command designating a copy source block number and a copy destination block number for garbage collection of the nonvolatile memory, to select a second block having the copy source block number and a third block having the copy destination block number, from the plural blocks, to determine a copy destination location in the third block to which valid data stored in the second block is to be written, to copy the valid data to the copy destination location in the third block, and to notify the host of a logical address of the valid data, the copy destination block number, and a second in-block physical address indicative of the copy destination location.

9. The memory system of claim 8 , wherein

the controller is configured, when the controller receives a read request designating the first block number and the first in-block physical address from the host, to read data from the first location in the first block, based on the first block number and the first in-block physical address.

10. The memory system of claim 8 , wherein

the first in-block physical address is represented by a first in-block offset indicative of an offset from a leading part of the first block to the first location by a multiple of grain having a size different from a page size, and

the second in-block physical address is represented by a second in-block offset indicative of an offset from a leading part of the third block to the copy destination location by a multiple of the grain.

11. The memory system of claim 8 , wherein

the controller is configured:

when receiving the write request from the host, to write the first logical address to the first block together with the data from the host; and

when receiving the control command from the host, to copy both of the valid data and a logical address of the valid data which are stored in the second block, to the third block.

12. A method of controlling a nonvolatile memory including plural blocks each including plural pages, the method comprising:

executing, when receiving a write request designating a first logical address and a first block number from a host, an operation of determining a first location in a first block having the first block number to which data from the host is to be written, an operation of writing the data from the host to the first location in the first block, and an operation of notifying the host of either a first in-block physical address indicative of the first location, or a group of the first logical address, the first block number, and the first in-block physical address; and

executing, when receiving from the host a control command designating a copy source block number and a copy destination block number for garbage collection of the nonvolatile memory, an operation of selecting a second block having the copy source block number and a third block having the copy destination block number, from the plural blocks, an operation of determining a copy destination location in the third block to which valid data stored in the second block is to be written, an operation of copying the valid data to the copy destination location in the third block, and an operation of notifying the host of a logical address of the valid data, the copy destination block number, and a second in-block physical address indicative of the copy destination location.

13. The method of claim 12 , further comprising:

when receiving a read request designating the first block number and the first in-block physical address from the host, reading data from the first location in the first block, based on the first block number and the first in-block physical address.

Assignments (4)
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 21, 2018
From: YOSHIDA, HIDEKI; KANNO, SHINICHI
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 045862/0482 →
Priority Claims (1)
JP 2017-208105 · Oct 27, 2017 · national
Continuity (1)
Related Publication 20190129838A1 · May 2, 2019