Fan-out semiconductor package

1. A fan-out semiconductor package comprising:

a frame including a plurality of insulating layers, a plurality of wiring layers disposed on the plurality of insulating layers, and a plurality of connection via layers penetrating through the plurality of insulating layers and electrically connecting the plurality of wiring layers to each other, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion;

a semiconductor chip disposed in the recess portion and having connection pads, an active surface on which the connection pads are disposed, and an inactive surface opposing the active surface and so that disposed on the stopper layer;

an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion;

a connection member disposed on the frame and the active surface of the semiconductor chip and including a redistribution layer electrically connecting the plurality of wiring layers of the frame and the connection pads of the semiconductor chip to each other; and

a guide pattern disposed adjacent to a wall of the recess portion and disposed in the frame,

wherein an edge of the bottom surface of the recess portion has a groove portion.

2. The fan-out semiconductor package of claim 1 , wherein the guide pattern is disposed on a level above the stopper layer, and

the groove portion is formed in the stopper layer.

3. The fan-out semiconductor package of claim 2 , wherein a region of the stopper layer having the groove portion has a thickness smaller than that of other regions of the stopper layer.

4. The fan-out semiconductor package of claim 1 , wherein the guide pattern is disposed on the same level as that of the stopper layer, and

the connection member further includes an insulating layer covering the guide pattern and the stopper layer and including a portion between the guide pattern and the stopper layer, the portion of the insulating layer between the guide pattern and the stopper layer having the groove portion.

5. The fan-out semiconductor package of claim 4 , wherein the guide pattern and the stopper layer are physically spaced apart from each other.

6. The fan-out semiconductor package of claim 5 , wherein the groove portion has a ring shape having a closed loop along the edge of the bottom surface of the recess portion.

7. The fan-out semiconductor package of claim 4 , wherein the guide pattern and the stopper layer have one or more connection portions connecting the guide pattern and the stopper layer to each other, and

the guide pattern, the stopper layer, and the one or more connection portions have two or more slits surrounded by the guide pattern, the stopper layer, and the one or more connection portions.

8. The fan-out semiconductor package of claim 7 , wherein the groove portion is a plurality of groove portions each formed along the edges of the bottom surface of the recess portion.

9. The fan-out semiconductor package of claim 1 , wherein each of the guide pattern and the stopper layer includes a metal,

at least one of the plurality of wiring layers includes a ground, and

at least one of the guide pattern and the stopper layer is electrically connected to the ground.

10. The fan-out semiconductor package of claim 1 , wherein the stopper layer has a planar area greater than that of the inactive surface of the semiconductor chip.

11. The fan-out semiconductor package of claim 1 , wherein the bottom surface of the recess portion has a planar area greater than that of the inactive surface of the semiconductor chip.

12. The fan-out semiconductor package of claim 1 , wherein the inactive surface of the semiconductor chip is attached to the stopper layer through an adhesive member.

13. The fan-out semiconductor package of claim 1 , wherein the wall of the recess portion is tapered.

14. The fan-out semiconductor package of claim 1 , wherein the wall of the recess portion has a plurality of different profiles.

15. The fan-out semiconductor package of claim 1 , further comprising metal bumps disposed on the connection pads of the semiconductor chip, and

upper surfaces of the metal bumps are coplanar with an upper surface of the encapsulant.

16. The fan-out semiconductor package of claim 15 , wherein an upper surface of an uppermost wiring layer of the plurality of wiring layers of the frame or an upper surface of an uppermost connection via layer of the plurality of connection via layers of the frame is coplanar with the upper surfaces of the metal bumps and the upper surface of the encapsulant.

17. The fan-out semiconductor package of claim 1 , wherein the plurality of insulating layers include a core insulating layer, one or more first build-up insulating layers disposed on a lower surface of the core insulating layer, and one or more second build-up insulating layers disposed on an upper surface of the core insulating layer, and

the core insulating layer has a thickness greater than that of each of the first and second build-up insulating layers.

18. The fan-out semiconductor package of claim 17 , wherein the number of first build-up insulating layers and the number of second build-up insulating layers are the same as each other.

19. The fan-out semiconductor package of claim 17 , wherein the recess portion penetrates through at least the core insulating layer and penetrates through at least one of the one or more second build-up insulating layers.

20. The fan-out semiconductor package of claim 17 , wherein the plurality of wiring layers include first connection vias penetrating through the first build-up insulating layer and second connection vias penetrating through the second build-up insulating layer, the first connection vias and the second connection vias being tapered in directions opposite to each other.

21. The fan-out semiconductor package of claim 1 , further comprising:

a first passivation layer disposed on the connection member and having openings exposing at least portions of the redistribution layer;

underbump metal layers disposed in the openings of the first passivation layer and connected to at least portions of the exposed redistribution layer; and

electrical connection structures disposed on the first passivation layer and connected to the underbump metal layers.

22. The fan-out semiconductor package of claim 1 , further comprising a second passivation layer disposed beneath the frame and having openings exposing at least portions of a lowermost wiring layer of the plurality of wiring layers.

23. The fan-out semiconductor package of claim 1 , wherein the encapsulant fills the groove portion.

24. The fan-out semiconductor package of claim 1 , wherein at least one of the wiring layers are disposed on the level below the stopper layer.