Memory processing unit
View Patent ↗An in-memory computing system for computing vector-matrix multiplications includes an array of resistive memory devices arranged in columns and rows, such that resistive memory devices in each row of the array are interconnected by a respective wordline and resistive memory devices in each column of the array are interconnected by a respective bitline. The in-memory computing system also includes an interface circuit electrically coupled to each bitline of the array of resistive memory devices and computes the vector-matrix multiplication between an input vector applied to a given set of wordlines and data values stored in the array. For each bitline, the interface circuit receives an output in response to the input being applied to the given wordline, compares the output to a threshold, and increments a count maintained for each bitline when the output exceeds the threshold. The count for a given bitline represents a dot-product.
1. An in-memory computing system for performing multiple-accumulate (MAC) operations and computing vector-matrix multiplications, the in-memory computing system comprising:
an array of resistive memory devices arranged in columns and rows, such that resistive memory devices in each row of the array are interconnected by a respective wordline and resistive memory devices in each column of the array are interconnected by a respective bitline, each resistive memory device in the array of resistive memory devices has an associated threshold voltage and is configured to store a data value therein as a resistance value; and
an interface circuit electrically coupled to each bitline of the array of resistive memory devices and cooperatively operates with the array of resistive memory devices to compute a vector-matrix multiplication between data values of a first vector as inputs applied to a set of wordlines and data values of a second vector stored in the array of resistive memory devices;
a plurality of comparators, wherein each comparator of the plurality of comparators is directly connected to a corresponding bitline, and wherein a respective comparator:
receives outputs on the given bitline in response to the inputs being applied to the set of wordlines; and
compares the outputs from the given bitline to a threshold associated with the respective comparator; and
a plurality of counters, wherein each counter of the plurality of counters is directly connected to a corresponding comparator of the plurality of comparators, and wherein each counter increments a count maintained for the given bitline when the comparison of the output for the given bitline exceeds the threshold associated with the respective comparator, such that the count for the given bitline represents the MAC operation performed between the data values of the first vector as inputs applied to the set of wordlines and the second vector stored in the array of resistive memory devices.
2. The in-memory computing system of claim 1 wherein a given input applied to a given wordline is a voltage applied to the given wordline as a pulse, and wherein the output on the given bitline is a current value.
3. The in-memory computing system of claim 2 wherein the given input is a series of pulses, and wherein a total of the series of pulses represents a non-binary value.
4. The in-memory computing system of claim 1 wherein the inputs are applied to the set of wordlines sequentially.
5. The in-memory computing system of claim 1 further comprising a decoder electrically coupled to each wordline, wherein the decoder is configured to apply the inputs to the set of wordlines.
6. The in-memory computing system of claim 1 wherein the second vector stored in the array of resistive memory devices comprises a feature vector.
7. The in-memory computing system of claim 1 wherein multiple resistive memory devices store multi-bit values in an identified bitline in the array of resistive memory devices.
8. The in-memory computing system of claim 1 wherein multiple arrays of resistive memory devices store multi-bit values.
9. An in-memory computing method for performing multiply-accumulate (MAC) operations and computing vector-matrix multiplications, the method comprising:
applying data values of a first vector as inputs to a set of wordlines of an array of resistive memory devices arranged in columns and rows, wherein the array is arranged such that resistive memory devices in each row of the array are interconnected by a respective wordline and resistive memory devices in each column of the array are interconnected by a respective bitline, and wherein each resistive memory device in the array of resistive memory devices has an associated threshold voltage and is configured to store a data value therein;
computing vector-matrix multiplication between the data values of the first vector applied as inputs to the given set of wordlines and the data values of a second vector stored in the array of resistive memory devices by, for each given bitline:
receiving, by a comparator directly connected to a corresponding bitline, outputs on the given bitline in response to the inputs being applied to the set of wordlines;
comparing, by the comparator directly connected to the corresponding bitline, the outputs from the given bitline to a threshold associated with the respective comparator; and
incrementing, by a counter directly connected to a corresponding comparator, a count for the given bitline when the comparison of the output for the given bitline exceeds the threshold, such that the count of the given bitline performs the MAC operation between the data values of the first vector as inputs applied to the set of wordlines and the second vector stored in the array of resistive memory devices.
10. The in-memory computing method of claim 9 wherein a given input applied to a given wordline is a voltage pulse, and wherein the output on the given bitline is a current value.
11. The in-memory computing method of claim 10 wherein the given input is a series of pulses, and wherein a total of series of pulses represents a non-binary value.
12. The in-memory computing method of claim 9 further comprising applying the inputs to the set of wordlines sequentially.
13. The in-memory computing method of claim 9 further comprising applying the inputs to the set of wordlines using a decoder.
14. The in-memory computing method of claim 9 wherein each device in the array of resistive memory devices stores the data values of the second vector as at least one of a resistance value and a conductance value.
15. An in-memory computing system for performing multiple-accumulate (MAC) operations and computing vector-matrix multiplications, the in-memory computing system comprising:
an array of resistive memory devices arranged in columns and rows, such that resistive memory devices in each row of the array are interconnected by a respective wordline and resistive memory devices in each column of the array are interconnected by a respective bitline, each resistive memory device in the array of resistive memory devices has an associated threshold voltage and is configured to store a data value therein as a resistance value; and
an interface circuit electrically coupled to each bitline of the array of resistive memory devices and cooperatively operates with the array of resistive memory devices to compute a vector-matrix multiplication between data values of a first vector as inputs applied to a set of wordlines and data values of a second vector stored in the array of resistive memory devices, where the interface circuit, for each given bitline:
receives outputs on the given bitline in response to the inputs being applied to the set of wordlines; and
compares the outputs from the given bitline to a threshold; and
wherein the interface circuit comprises a plurality of counters, wherein each counter of the plurality of counters is electrically connected to a corresponding bitline, and wherein each counter increments a count maintained for the given bitline when the comparison of the output for the given bitline exceeds the threshold, such that the count for the given bitline represents the MAC operation performed between the data values of the first vector as inputs applied to the set of wordlines and the second vector stored in the array of resistive memory devices.
16. The in-memory computing system of claim 15 wherein the given input is a series of pulses, and wherein a total of the series of pulses represents a non-binary value.
17. The in-memory computing system of claim 15 wherein the inputs are applied to the set of wordlines sequentially.
18. The in-memory computing system of claim 15 further comprising a decoder electrically coupled to each wordline, wherein the decoder is configured to apply the inputs to the set of wordlines.
19. The in-memory computing system of claim 15 wherein the second vector stored in the array of resistive memory devices comprises a feature vector.
20. The in-memory computing system of claim 15 wherein multiple resistive memory devices store multi-bit values in an identified bitline in the array of resistive memory devices.