IP Library › Granted Patent US 10,284,192
Granted Patent B2
US 10,284,192 · App. 15/986,367 · Granted May 7, 2019

Semiconductor device

Inventor: Masashi Akahane (Matsumoto, JP)
Assignee: FUJI ELECTRIC CO., LTD.
H03K17/0828G11C16/0408G11C16/10G11C16/12G11C16/26G11C16/32G11C29/021G11C29/028G11C29/48G11C29/50G11C29/56012G11C2029/5002G11C2029/5004G11C2029/5602H03K2017/0806
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Quick Facts
Patent No.
US 10,284,192
App. No.
15/986,367
Granted
May 7, 2019
Kind
B2
Abstract

A semiconductor device including a first control circuit, a memory and a second control circuit. The first control circuit includes a monitoring section which receives a voltage signal which includes a pulse signal having a plurality of different voltage levels superimposed on a power source voltage, monitors a level of the voltage signal and outputs a monitoring result, and a regulator which generates an internal voltage. The memory receives the internal voltage. The second control circuit receives the internal voltage, reproduces a clock and data from the pulse signal on the basis of the monitoring result, and performs trimming on the memory using the clock and the data.

Claims (73)

1. A semiconductor device comprising:

a terminal configured to receive a voltage signal which includes a pulse signal having a plurality of different voltage levels superimposed on a power source voltage;

a first control circuit including

a monitoring section which

receives the voltage signal from the terminal,

monitors a level of the voltage signal, and

outputs a monitoring result, and

a regulator which generates an internal voltage;

a memory which receives the internal voltage; and

a second control circuit which

receives the internal voltage,

receives the voltage signal,

reproduces a clock and data from the pulse signal having the plurality of different voltage levels, on the basis of the monitoring result, and

performs trimming on the memory using the clock and the data.

2. The semiconductor device according to claim 1 , wherein

the first control circuit has an external element connected thereto, for performing drive control of the external element; and

the monitoring section

determines that a range in which the level of the voltage signal is higher than a predetermined threshold is an operation range for the drive control of the external element, and

determines that a range in which the level of the voltage signal is between a starting voltage of the regulator and the threshold is an operation range for control of the trimming.

3. The semiconductor device according to claim 2 , further comprising:

a first switch which receives the monitoring result and outputs a switching signal according to a value of the monitoring result, wherein

the monitoring section outputs a first monitoring result at a time when the level of the voltage signal is higher than the threshold and outputs a second monitoring result at a time when the level of the voltage signal is between the starting voltage of the regulator and the threshold;

responsive to the first monitoring result, the first switch outputs a stop signal as the switching signal to the second control circuit, to cause the second control circuit to stop the trimming and to cause the first control circuit to perform the drive control of the external element; and

responsive to the second monitoring result, the first switch applies to the second control circuit the pulse signal as the switching signal, to cause the second control circuit to perform the trimming and to cause the first control circuit to stop the drive control of the external element, the voltage levels of the pulse signal being between the starting voltage of the regulator and the threshold.

4. The semiconductor device according to claim 3 , further comprising:

a second switch which

receives alarm data from the first control circuit and memory data from the memory via the second control circuit at the time of the trimming, and

switches an output,

the alarm data indicating a state of the external element, wherein

the second control circuit

receives the switching signal,

outputs a first select signal at a time when the switching signal is a ground, and

outputs a second select signal at a time when the switching signal is the pulse signal; and

the second switch

outputs the alarm data from a single terminal responsive to the first select signal, and

outputs the memory data from the single terminal responsive to the second select signal.

5. The semiconductor device according to claim 1 , wherein:

the second control circuit includes a switch which

receives a write setting signal indicative of whether to write the data to the memory at a time of the trimming and a drive signal for driving an external element, and

switches an output;

when the write setting signal is in an off state, the switch outputs the drive signal from a single terminal to the external element; and

when the write setting signal is in an on state, the switch applies a predetermined voltage inputted from the single terminal to the memory.

6. A semiconductor device, comprising:

a first control circuit including

a monitoring section which

receives a voltage signal which includes a pulse signal having a plurality of different voltage levels superimposed on a power source voltage,

monitors a level of the voltage signal, and

outputs a monitoring result, and

a regulator which generates an internal voltage;

a memory which receives the internal voltage; and

a second control circuit which

receives the internal voltage,

reproduces a clock and data from the pulse signal on the basis of the monitoring result, and

performs trimming on the memory using the clock and the data, wherein:

the semiconductor device is connectable to a switch and a capacitor disposed outside the semiconductor device, one end of the switch being connected to a line along which the voltage signal flows, another end of the switch being connected to one end of the capacitor, another end of the capacitor being connected to a ground;

at a time of drive control of an external element, the switch is turned on on the basis of external instructions, to connect the one end of the capacitor to the line; and

at a time of the trimming, the switch is turned off on the basis of the external instructions, to disconnect the one end of the capacitor from the line.

7. A semiconductor, comprising:

a first control circuit including

a monitoring section which

receives a voltage signal which includes a pulse signal having a plurality of different voltage levels superimposed on a power source voltage,

monitors a level of the voltage signal, and

outputs a monitoring result, and

a regulator which generates an internal voltage;

a memory which receives the internal voltage; and

a second control circuit which

receives the internal voltage,

reproduces a clock and data from the pulse signal on the basis of the monitoring result, and

performs trimming on the memory using the clock and the data, wherein

the monitoring section

sets a range in which the level of the voltage signal is higher than a first predetermined threshold, as an operation range for drive control of an external element;

sets a range in which the level of the voltage signal is between a starting voltage of the regulator and a second predetermined threshold, as an operation range for control of the trimming; and

recognizes, as a voltage abnormality state, a state in which the level of the voltage signal is between the first threshold and the second threshold for a predetermined period.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 22, 2018
From: AKAHANE, MASASHI
To: FUJI ELECTRIC CO., LTD.
Reel/Frame 045874/0608 →
Priority Claims (1)
JP 2016-111851 · Jun 3, 2016 · national
Continuity (2)
Continuation PCTJP2017016730 · Apr 27, 2017
Related Publication 20180269864A1 · Sep 20, 2018