Semiconductor package

1. A semiconductor package comprising:

a semiconductor chip having connection pads;

a connection member having a first surface on which the semiconductor chip is disposed and a second surface opposing the first surface, and including an insulating member and a redistribution layer disposed in the insulating member to be electrically connected to the connection pads;

an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip;

an organic barrier layer disposed as an outermost layer on the second surface of the connection member and including an organic material containing fluorine;

electrical connection structures disposed on the second surface of the connection member; and

underbump metallurgy (UBM) layers connecting the electrical connection structures and the redistribution layer to each other,

wherein the organic barrier layer covers surfaces of the electrical connection structures, and a thickness of the organic barrier layer is 0.2 μm or less.

2. The semiconductor package of claim 1 , wherein the organic material includes at least one selected from the group consisting of CF 4 , C 4 F 8 , and fluoroalkyl silane.

3. The semiconductor package of claim 1 , wherein the thickness of the organic barrier layer is 0.02 μm or greater.

4. The semiconductor package of claim 1 , wherein the insulating member is formed of a photosensitive organic material.

5. The semiconductor package of claim 1 , further comprising a core member disposed on the first surface of the connection member and having a cavity in which the semiconductor chip is accommodated.

6. The semiconductor package of claim 5 , wherein the core member has a wiring structure connecting upper and lower surfaces of the core member to each other and electrically connected to the redistribution layer.

7. The semiconductor package of claim 1 , wherein the organic material further comprises perylene.

8. A semiconductor package comprising:

a semiconductor chip having connection pads;

a connection member having a first surface on which the semiconductor chip is disposed and a second surface opposing the first surface and including an insulating member, a redistribution layer disposed in the insulating member to be electrically connected to the connection pads, and UBM layers electrically connected to the redistribution layer and providing connection regions on the second surface;

an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip;

electrical connection structures disposed on the second surface of the connection member and connected to the connection regions of the UBM layers; and

a multilayer barrier having an organic layer disposed on the second surface of the connection member and an inorganic layer disposed as an outermost layer on the organic layer.

9. The semiconductor package of claim 8 , wherein the organic layer is an organic layer containing fluorine, and

the inorganic layer includes at least one selected from the group consisting of silicon oxide, silicon nitride, and silicon oxynitride.

10. The semiconductor package of claim 8 , wherein an oxygen permeability of the multilayer barrier is 0.01 cc/m 2 /day or less.

11. The semiconductor package of claim 8 , wherein a water vapor permeability of the multilayer barrier is 0.1 g/m 2 /day or less.

12. The semiconductor package of claim 9 , wherein the organic layer includes an organic material satisfying R—Si—F x C y OH, where R is an alkyl, fluoroalkyl, acryl, methacryl, vinyl, epoxy, amine, or aniline group.

13. The semiconductor package of claim 8 , wherein a thickness of the organic layer is within a range from 0.01 to 0.5 μm, inclusive, and

a thickness of the inorganic layer is within a range from 0.01 to 0.5 μm, inclusive.

14. The semiconductor package of claim 8 , wherein a thickness of the organic layer is greater than a thickness of the inorganic layer.