Method of forming semiconductor memory device
A method of forming semiconductor memory device includes the following steps. Firstly, a substrate is provided and the substrate includes a cell region. Then, plural bit lines are disposed within the cell region along a first direction, with each of the bit line includes a tri-layered spacer structure disposed at two sides thereof. Next, plural of first plugs are formed within the cell region, with the first plugs being disposed at two sides of each bit lines. Furthermore, plural conductive patterns are formed in alignment with each first plugs. Following theses, a chemical reaction process is performed to modify the material of a middle layer of the tri-layered spacer structure, and a heat treatment process is performed then to remove the modified middle layer, thereto form an air gap layer within the tri-layered spacer structure.
1. A method of forming a semiconductor memory device, comprising:
providing a substrate, the substrate comprising a periphery region and a memory cell region;
forming a plurality of bit lines extended along a first direction on the substrate, within the memory cell region, wherein a spacer structure is formed at two sides of each of the bit lines and the spacer structure comprises a tri-layer structure;
forming a plurality of first plugs on the substrate within the memory cell region, at two sides of each of the bit lines;
forming a gate structure on the substrate within the periphery region, the gate structure extended along a second direction being perpendicular to the first direction;
forming a plurality of conductive patterns, the conductive patterns being in alignment and directly in contact with the first plugs;
forming a plurality of second plugs on the substrate within the periphery region, the second plugs being electrically connected to two source/drain regions respectively at two sides of the gate structure, wherein the second plugs and the first plugs are formed simultaneously;
after forming the conductive patterns, performing a chemical reaction process, to transform a second spacer of the tri-layer structure of the spacer structure to form a transformed second spacer; and
removing the transformed second spacer to form an air-gap layer in the spacer structure.
2. The method of forming a semiconductor memory device according to claim 1 , wherein the gate structure and the bit lines are formed simultaneously.
3. The method of forming a semiconductor memory device according to claim 1 , wherein the conductive patterns are formed in an array arrangement, and the conductive patterns are electrically connected to the first plugs within the memory cell region and the second plugs within the periphery region.
4. The method of forming a semiconductor memory device according to claim 1 , further comprising:
before performing the chemical reaction, forming a mask layer on the substrate within the periphery region, to cover the gate structure and the second plugs.
5. The method of forming a semiconductor memory device according to claim 4 , wherein after removing the transformed second spacer, the mask layer is completely removed.
6. The method of forming a semiconductor memory device according to claim 1 , wherein the second spacer comprises silicon oxide.
7. The method of forming a semiconductor memory device according to claim 1 , wherein the chemical reaction is performed by providing a reagent to transform the second spacer into ammonium hexafluorosilicate.
8. The method of forming a semiconductor memory device according to claim 7 , wherein the reagent comprises nitrogen gas, hydrogen gas and nitrogen trifluoride gas.
9. The method of forming a semiconductor memory device according to claim 7 , wherein the reagent comprises ammonium fluoride.
10. The method of forming a semiconductor memory device according to claim 1 , further comprising:
performing a heat treatment process after the chemical reaction process, to remove the transformed second spacer.
11. The method of forming a semiconductor memory device according to claim 10 , wherein the heat treatment process is performed at a temperature ranged from 100 degrees Celsius to 150 degrees Celsius to vaporize the transformed second spacer.