Method and system for signal detection including positioning signals
An assisted satellite positioning system based on detecting signals from a number of satellites includes: (a) a mobile receiver; and (b) a base station communicating with the receiver over a low-power wireless communication network, the base station providing ephemeris data of a selected number of the satellites, but not all, using a compressed data format. The ephemeris data may include data concerning doppler frequency variations or elevation variations of the selected satellites over a predetermined time interval. The doppler frequency variations and the elevation variations may be represented in the compressed format by coefficients of a polynomial function of time. The polynomial function may be weighted to have lesser relative errors in larger doppler frequencies than lesser doppler frequencies, or to have lesser relative errors in lesser elevations than larger elevations. In one implementation, the low-power wireless communication network—such as a LoRa network—that has a range of at least 10 miles.
1. A signal processing device for detecting a spread spectrum signal modulated with a pseudorandom code of a predetermined number of chips, comprising:
a temperature-compensated crystal oscillator providing a timing signal accurate to a predetermined fraction of one of the chips;
a clock generator receiving the timing signal to generate a first digital clock signal of a predetermined frequency;
an analog signal processing circuit receiving the timing signal and the spread spectrum signal and providing digital baseband samples of the spread spectrum signal at each period of a second digital clock signal;
a counter circuit receiving the first digital clock signal to provide a timing pulse of a predetermined duration;
a data buffer;
an input interface circuit for the data buffer, receiving the digital baseband samples, the second digital clock signal and the timing pulse, and storing the digital baseband samples into the data buffer over the predetermined duration; and
a processor which retrieves the stored baseband samples from the data buffer to perform signal detection.
2. The signal processing device of claim 1 , wherein the input interface circuit comprises a plurality of parallel-connected serial peripheral interface circuits.
3. The signal processing device of claim 1 , wherein the predetermined frequency of the second digital clock signal is 16 MHz.
4. The signal processing device of claim 1 , wherein the second digital clock signal is accurate to 1/16 μs.
5. The signal processing device of claim 1 , wherein the processor enters a sleep state upon completion of the signal detection.
6. The signal processing device of claim 1 , wherein the processor, the data buffer and the input interface circuit are elements of an embedded microcontroller integrated circuit.
7. The signal processing device of claim 1 , wherein the digital baseband samples comprise samples of in-phase and quadrature channels of a baseband signal.
8. The signal processing device of claim 1 , further comprising a housing in which the temperature-compensated crystal oscillator, the clock generator, the analog signal processing circuit, the counter, the input interface circuit, the data buffer and the processor are mounted.
9. The signal processing device of claim 8 further comprising a battery, a power-regulation circuit for the battery and a solar panel converting solar energy into energy in the battery under control of the power-regulation circuit, the solar panel being mounted on an outside surface of the housing.
10. The signal processing device of claim 1 , further comprising a communication module for communicating over a low power wide area network.
11. The signal processing device of claim 10 , wherein the low power wide area network comprises a LoRa network.