FinFETs and methods of forming FinFETs
An embodiment is a method including recessing a gate electrode over a semiconductor fin on a substrate to form a first recess from a top surface of a dielectric layer, forming a first mask in the first recess over the recessed gate electrode, recessing a first conductive contact over a source/drain region of the semiconductor fin to form a second recess from the top surface of the dielectric layer, and forming a second mask in the second recess over the recessed first conductive contact.
1. A structure comprising:
a first fin over a substrate;
an isolation region surrounding lower surfaces of the first fin;
a gate structure along sidewalls and over upper surfaces of the first fin;
a source/drain region on the first fin adjacent the gate structure;
a dielectric layer over the isolation region and surrounding the gate structure;
a first mask over the gate structure, the first mask having a top surface level with a top surface of the dielectric layer;
a first conductive contact through the dielectric layer to contact the source/drain region; and
a second mask over the first conductive contact, the second mask having a top surface level with the top surface of the dielectric layer.
2. The structure of claim 1 further comprising:
a liner insulation layer interposed between the first conductive contact and the second mask.
3. The structure of claim 2 , wherein the liner insulation layer is a metallic oxide or metallic nitride comprising aluminum, titanium, hafnium, zirconium, tantalum, or a combination thereof, and wherein the second mask comprises silicon oxynitride, silicon carbide, carbon-containing silicon oxide, or a combination thereof.
4. The structure of claim 1 , wherein a material composition of the first mask is different from a material composition of the second mask.
5. The structure of claim 1 , wherein the first mask comprises silicon nitride.
6. The structure of claim 5 , wherein the second mask comprises silicon oxynitride, silicon carbide, or a combination thereof.
7. The structure of claim 1 further comprising:
a second conductive contact extending through the second mask, the second conductive contact electrically coupled to the first conductive contact; and
a third conductive contact extending through the first mask, the third conductive contact electrically coupled to the gate structure.
8. The structure of claim 7 , wherein the second conductive contact, the second mask, and the dielectric layer have level top surfaces.
9. A fin field effect transistor (FinFET) comprising:
a first fin over a substrate;
an isolation region surrounding lower surfaces of the first fin;
a gate structure on the first fin and the isolation region;
a source/drain region on the first fin adjacent the gate structure;
a dielectric layer over the isolation region and the source/drain region;
a first mask over the gate structure;
a first conductive contact through the dielectric layer to contact the source/drain region; and
a second mask over the first conductive contact, the second mask having a top surface level with a top surface of the dielectric layer, wherein a material composition of the first mask is different from a material composition of the second mask.
10. The FinFET of claim 9 , wherein top surfaces of the first mask, the second mask, and the dielectric layer are level with each other.
11. The FinFET of claim 9 further comprising:
a liner insulation layer interposed between the first conductive contact and the second mask.
12. The FinFET of claim 11 further comprising:
a second conductive contact extending through the second mask and the liner insulation layer, the second conductive contact electrically coupled to the first conductive contact.
13. The FinFET of claim 9 , wherein the first mask comprises silicon nitride.
14. The FinFET of claim 9 , wherein the second mask comprises silicon oxynitride, silicon carbide, or a combination thereof.
15. A device comprising:
a first fin over a substrate;
an isolation region surrounding lower surfaces of the first fin;
a gate dielectric and a gate electrode over the first fin and the isolation region;
a source/drain region on the first fin adjacent the gate dielectric and the gate electrode;
a dielectric layer over the isolation region and the source/drain region;
a first mask over the gate dielectric and the gate electrode;
a first conductive contact in the dielectric layer to contact the source/drain region;
a liner insulation layer over the first conductive contact and adjoining the dielectric layer; and
a second mask over the first conductive contact, the liner insulation layer being interposed between the first conductive contact and the second mask.
16. The device of claim 15 , wherein the first mask physically contacts the gate dielectric and the gate electrode.
17. The device of claim 15 , wherein the first mask, the second mask, and the dielectric layer have coplanar top surfaces.
18. The device of claim 15 , wherein the liner insulation layer is a metallic oxide or metallic nitride comprising aluminum, titanium, hafnium, zirconium, tantalum, or a combination thereof, and wherein the second mask comprises silicon oxynitride, silicon carbide, carbon-containing silicon oxide, or a combination thereof.
19. The device of claim 15 , wherein a material composition of the first mask is different from a material composition of the second mask.
20. The device of claim 15 further comprising:
a second conductive contact extending through the second mask and the liner insulation layer, the second conductive contact electrically coupled to the first conductive contact.