Bottom electrode for MRAM applications
A substantially flat bottom electrode for magnetoresistive random access memory (MRAM) devices includes three components: a recessed bulk conductive material such as copper, a conductive liner lining the recess, and a cap layer, wherein the conductive liner is a harder material than the cap layer. The cap layer and the dielectric layer are coplanar having a height differential of less than 3 nanometers. The conductive liner has a lower chemical mechanical planarization removal rate. Also provided are processes for forming the bottom electrode.
1. A process of forming a bottom electrode in a magnetoresistive random access memory (MRAM) device, the process comprising:
providing a structure comprising a dielectric layer including a patterned feature lined with a barrier layer and a metal conductor;
planarizing a surface of the structure stopping at the dielectric layer to remove an overburden of the metal conductor;
forming a recess in the metal conductor;
depositing a conductive liner material in the recess of the metal conductor and on the dielectric layer;
depositing tantalum nitride cap layer in the recess on the conductive liner material and on the dielectric layer; and
polishing the tantalum nitride cap layer to the dielectric layer with a chemical mechanical planarization process to form the bottom electrode, wherein a height differential between upper surfaces of the tantalum nitride cap layer and the dielectric layer is less than 3 nanometers, wherein the conductive liner material is harder than the tantalum nitride.
2. The process of claim 1 , wherein the conductive liner material comprises ruthenium.
3. The process of claim 1 , wherein the conductive liner material comprises ruthenium, rhodium, or combinations comprising at least one of the foregoing.
4. The process of claim 1 , wherein the conductive liner material has a lower chemical mechanical planarization removal rate than the tantalum nitride.
5. The process of claim 1 , wherein the metal conductor comprise copper, aluminum, tantalum, tungsten, tantalum nitride (TaN), titanium, titanium nitride (TiN), and/or a combination thereof.
6. The process of claim 1 , wherein the conductive liner material is at a thickness of 1 to 10 nanometers.
7. The process of claim 1 , wherein the conductive liner has a hardness greater than about 12 gigapascals.
8. The process of claim 1 , wherein the conductive liner material is at a thickness of 0.5 nanometers to 50 nanometers.
9. The process of claim 1 , wherein the conductive liner material is at a thickness of 1 nanometer to 20 nanometers.
10. The process of claim 1 , wherein depositing the conductive liner material in the recess conductive liner comprises conformally depositing the conductive liner material.
11. The process of claim 1 , wherein the height differential between the tantalum nitride surface and the dielectric layer surface is less than 2 nanometers.
12. The process of claim 1 wherein a height differential between the tantalum nitride surface and the dielectric layer surface is less than 1 nanometer.
13. The process of claim 1 , wherein the conductive liner is deposited in situ when depositing the tantalum nitride capping layer.