Display device

1. A display device, comprising:

a substrate comprising a display area and a non-display area adjacent to the display area;

an anode electrode positioned in the display area;

an organic light emitting layer disposed on the anode electrode and positioned in the display area;

a cathode electrode disposed on the organic light emitting layer;

a gate driver positioned in the display area;

a lower first insulator;

a lower second insulator;

a lower protective layer; and

a lower planarizing layer,

wherein:

the G-semiconductor layer is disposed on the substrate;

the lower first insulator is disposed on the substrate and covers the G-semiconductor layer;

the G-gate electrode is disposed on the lower first insulator;

the lower second insulator is disposed on the lower first insulator and covers the G-gate electrode;

the G-source electrode is disposed on the lower second insulator and passes through the lower first and second insulators, wherein the G-source electrode is connected to an upper surface of the G-semiconductor layer;

the G-drain electrode is disposed on the lower second insulator and passes through the lower first and second insulators, wherein the G-drain electrode is connected to the upper surface of the G-semiconductor layer and is spaced apart from the G-source electrode;

the lower protective layer is disposed on the lower second insulator and covers the G-source electrode and the G-drain electrode; and

the lower planarizing layer is disposed on the lower protective layer.

2. The display device of claim 1 , further comprising:

an upper first insulator;

an upper second insulator;

an upper protective layer; and

an upper planarizing layer,

wherein:

the D-semiconductor layer is disposed on the lower planarizing layer;

the upper first insulator is disposed on the lower planarizing layer and covers the D-semiconductor layer;

the D-gate electrode is disposed on the upper first insulator and is connected to the G-drain electrode;

the upper second insulator is disposed on the upper first insulator and covers the D-gate electrode;

the D-source electrode is disposed on the upper second insulator and passes through the upper first and second insulators, wherein the D-source electrode is connected to the D-semiconductor layer;

the D-drain electrode is disposed on the upper second insulator and passes through the upper first and second insulators, wherein the D-drain electrode is connected to the D-semiconductor layer and is spaced apart from the D-source electrode;

the upper protective layer is disposed on the upper second insulator and covers the D-source electrode and the D-drain electrode;

the upper planarizing layer is disposed on the upper protective layer; and

the anode electrode is disposed on the upper planarizing layer and connected to the D-drain electrode.

3. The display device of claim 2 , wherein the D-semiconductor layer comprises a first D-semiconductor layer and a second D-semiconductor layer,

wherein the first D-semiconductor layer is spaced apart from the second D-semiconductor layer,

wherein the D-source electrode is connected to the first D-semiconductor layer, and

wherein the D-drain electrode is connected to the second D-semiconductor layer.

4. The display device of claim 1 , further comprising:

an upper first insulator;

an upper protective layer; and

an upper planarizing layer,

wherein the driving TFT further comprises a D-etch stopper layer, and

wherein:

the D-gate electrode is disposed on the lower planarizing layer;

the upper first insulator is disposed on the lower planarizing layer and covers the D-gate electrode;

the D-semiconductor layer is disposed on the upper first insulator;

the D-etch stopper layer is disposed on the D-semiconductor layer;

the D-source electrode is disposed on the upper first insulator and covers a side of the D-semiconductor layer and a side of the D-etch stopper layer;

the D-drain electrode is disposed on the upper first insulator and covers another side of the D-semiconductor layer and another side of the D-etch stopper layer;

the upper protective layer is disposed on the upper first insulator and covers the D-source electrode and the D-drain electrode;

the upper planarizing layer is disposed on the upper protective layer; and

the anode electrode is disposed on the upper planarizing layer and connected to the D-drain electrode.

5. The display device of claim 1 , further comprising a data driver positioned in the non-display area and electrically connected to the gate driver.

6. The display device of claim 5 , wherein the data driver comprises:

a first data driver; and

a second data driver spaced apart from the first data driver.

7. The display device of claim 5 , further comprising a source COF (Chip On Film) positioned in the non-display area and configured to connect the data driver to the substrate.

8. A display device, comprising:

a substrate comprising a display area and a non-display area adjacent to the display area;

an anode electrode positioned in the display area;

an organic light emitting layer disposed on the anode electrode and positioned in the display area;

a cathode electrode disposed on the organic light emitting layer;

a gate driver positioned in the display area;

a driving TFT (thin film transistor) positioned in the display area, wherein the driving TFT comprises:

a D-drain electrode connected to the anode electrode;

a D-source electrode;

a D-gate electrode; and

a D-semiconductor layer,

wherein the gate driver comprises a plurality of gate TFTs disposed on the gate driver and the gate driver is disposed on the substrate,

wherein each of the plurality of gate TFTs comprises:

a G-semiconductor layer;

a G-gate electrode;

a G-source electrode; and

a G-drain electrode connected to the D-gate electrode,

wherein the display device further comprises:

a lower first insulator;

a lower protective layer; and

a lower planarizing layer,

wherein the gate TFT further comprises a G-etch stopper layer, and

wherein:

the G-gate electrode is disposed on the substrate;

the lower first insulator is disposed on the substrate and covers the G-gate electrode;

the G-semiconductor layer is disposed on the lower first insulator;

the G-etch stopper layer is disposed on the G-semiconductor layer;

the G-source electrode is disposed on the lower first insulator and covers a side of the G-semiconductor layer and a side of the G-etch stopper layer;

the G-drain electrode is disposed on the lower first insulator and covers another side of the G-semiconductor layer and another side of the G-etch stopper layer;

the lower protective layer is disposed on the lower first insulator and covers the D-source electrode and the D-drain electrode; and

the lower planarizing layer is disposed on the lower protective layer.

9. The display device of claim 8 , further comprising:

an upper first insulator;

an upper second insulator;

an upper protective layer; and

an upper planarizing layer,

wherein:

the D-semiconductor layer is disposed on the lower planarizing layer;

the upper first insulator is disposed on the lower planarizing layer and covers the D-semiconductor layer;

the D-gate electrode is disposed on the upper first insulator;

the upper second insulator is disposed on the upper first insulator and covers the D-gate electrode;

the D-source electrode is disposed on the upper second insulator and passes through the upper first and second insulators, wherein the D-source electrode is connected to the D-semiconductor layer;

the D-drain electrode is disposed on the upper second insulator and passes through the upper first and second insulators, wherein the D-drain electrode is connected to the D-semiconductor layer and is spaced apart from the D-source electrode;

the upper protective layer is disposed on the upper second insulator and covers the D-source electrode and the D-drain electrode;

the planarizing layer is disposed on the upper protective layer; and

the anode electrode is disposed on the upper planarizing layer and is connected to the D-drain electrode.

10. The display device of claim 9 , wherein the D-semiconductor layer comprises a first D-semiconductor layer and a second D-semiconductor layer,

wherein the first D-semiconductor layer is spaced apart from the second D-semiconductor layer,

wherein the D-source electrode is connected to the first D-semiconductor layer, and

wherein the D-drain electrode is connected to the second D-semiconductor layer.

11. The display device of claim 8 , further comprising:

an upper first insulator;

an upper protective layer; and

an upper planarizing layer,

wherein the driving TFT includes a D-etch stopper layer,

wherein:

the D-gate electrode is disposed on the lower planarizing layer;

the upper first insulator is disposed on the lower planarizing layer and covers the D-gate electrode;

the D-semiconductor layer is disposed on the upper first insulator;

the D-etch stopper layer is disposed on the D-semiconductor layer;

the D-source electrode is disposed on the upper first insulator and covers a side of the D-semiconductor layer and a side of the D-etch stopper layer;

the D-drain electrode is disposed on the upper first insulator and covers another side of the D-semiconductor layer and another side of the D-etch stopper layer;

the upper protective layer is disposed on the upper first insulator and covers the D-source electrode and the D-drain electrode;

the upper planarizing layer is disposed on the upper protective layer; and

the anode electrode is disposed on the upper planarizing layer and is connected to the D-drain electrode.

12. The display device of claim 8 , further comprising a data driver positioned in the non-display area and electrically connected to the gate driver.

13. The display device of claim 12 , wherein the data driver comprises:

a first data driver; and

a second data driver spaced apart from the first data driver.

14. The display device of claim 12 , further comprising a source COF (Chip On Film) positioned in the non-display area and configured to connect the data driver to the substrate.