Fan-out semiconductor package
A fan-out semiconductor package includes a first connection member having a through-hole, a semiconductor chip disposed in the through-hole and including an active surface having connection pads disposed thereon and an inactive surface opposing the active surface, a second connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the semiconductor chip, and an encapsulant encapsulating the semiconductor chip and having a cavity disposed above the inactive surface of the semiconductor chip.
1. A fan-out semiconductor package comprising:
a first connection member having a through-hole;
a first semiconductor chip disposed in the through-hole and including an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;
a second connection member disposed on the active surface of the first semiconductor chip and including a redistribution layer electrically connected to the first semiconductor chip; and
an encapsulant filling spaces between wall surfaces of the through-hole and side surfaces of the first semiconductor chip and having a cavity disposed above the inactive surface of the first semiconductor chip,
wherein the cavity is a recess in the encapsulant defined by an inner lower surface of the encapsulant disposed between an uppermost surface of the encapsulant and a lowermost surface of the encapsulant, and an inner side surface of the encapsulant connecting the uppermost surface of the encapsulant and the inner lower surface of the encapsulant,
the uppermost surface of the encapsulant is substantially coplanar with an upper surface of the first connection member,
the lowermost surface of the encapsulant is at a lower level than a lower surface of the first connection member.
2. The fan-out semiconductor package of claim 1 , further comprising an adhesive layer disposed on the inactive surface of the first semiconductor chip,
wherein the inner lower surface is substantially coplanar with an upper surface of the adhesive layer.
3. The fan-out semiconductor package of claim 1 , wherein the cavity has a first width greater than a second width of the first semiconductor chip.
4. The fan-out semiconductor package of claim 1 , further comprising a heat radiation portion disposed in the cavity and bonded to the first semiconductor chip.
5. The fan-out semiconductor package of claim 1 , wherein the encapsulant does not cover the inactive surface of the first semiconductor chip.
6. The fan-out semiconductor package of claim 1 , wherein the cavity exposes entirely the inactive surface of the first semiconductor chip.