Transistors with dual gate conductors, and associated methods
A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor includes a silicon semiconductor structure and a vertical gate. The vertical gate includes (a) a first gate conductor and a second gate conductor each extending from a first outer surface of the silicon semiconductor structure into the silicon semiconductor structure in a thickness direction, (b) a first separation dielectric layer separating the first gate conductor from the second gate conductor within the vertical gate, and (c) a gate dielectric layer separating each of the first gate conductor and the second gate conductor from the silicon semiconductor structure.
1. A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor, comprising:
a silicon semiconductor structure; and
a vertical gate, including:
a first gate conductor and a second gate conductor each extending from a first outer surface of the silicon semiconductor structure into the silicon semiconductor structure in a thickness direction,
a first separation dielectric layer separating the first gate conductor from the second gate conductor within the vertical gate in each of the thickness direction and a lateral direction, the lateral direction being orthogonal to the thickness direction, and
a gate dielectric layer separating each of first the gate conductor and the second gate conductor from the silicon semiconductor structure, wherein:
the gate dielectric layer separates the first gate conductor from a first source region of the LDMOS transistor by a separation distance t 2 in the lateral direction,
the gate dielectric layer separates the second gate conductor from the first source region of the LDMOS transistor by a separation distance t 3 in the lateral direction, and
the separation distance t 2 is greater than the separation distance t 3 .
2. The LDMOS transistor of claim 1 , wherein the first gate conductor is adjacent to a drain region of the LDMOS transistor in the lateral direction.
3. The LDMOS transistor of claim 2 , wherein the second gate conductor is adjacent to the first source region of the LDMOS transistor in the lateral direction.
4. The LDMOS transistor of claim 1 , wherein:
the silicon semiconductor structure includes:
a base layer,
an n-type layer disposed over the base layer in the thickness direction,
a p-body region disposed in the n-type layer,
a source n+ region disposed in the p-body region, and
a drain n+ region disposed in the n-type layer; and
each of the first gate conductor and the second gate conductor is disposed between the source n+ region and the drain n+ region in the lateral direction.
5. The LDMOS transistor of claim 4 , further comprising:
a source electrode electrically coupled to the source n+region;
a drain electrode electrically coupled to the drain n+region; and
a first gate electrode electrically coupled to the first gate conductor.
6. The LDMOS transistor of claim 5 , wherein the first gate electrode is additionally electrically coupled to the second gate conductor.
7. The LDMOS transistor of claim 5 , further comprising a second gate electrode electrically coupled to the second gate conductor.
8. The LDMOS transistor of claim 4 , further comprising a p-type reduced surface field effect (RESURF) layer disposed below the vertical gate in the thickness direction.
9. The LDMOS transistor of claim 1 , wherein the vertical gate further includes:
a third gate conductor; and
a second separation dielectric layer separating the first gate conductor from the third gate conductor within the vertical gate.
10. The LDMOS transistor of claim 9 , wherein the second separation dielectric layer separates the first gate conductor from the third gate conductor in the thickness direction.
11. The LDMOS transistor of claim 9 , wherein the gate dielectric layer further separates the third gate conductor from the silicon semiconductor structure.
12. The LDMOS transistor of claim 9 , wherein:
the first gate conductor is adjacent to a drain region of the LDMOS transistor in the lateral direction;
the second gate conductor is adjacent to the first source region of the LDMOS transistor in the lateral direction; and
the third gate conductor is adjacent to a well region of the LDMOS transistor in the thickness direction.
13. An integrated circuit, comprising:
the LDMOS transistor of claim 1 ; and
a trench capacitor, including:
a first capacitor conductor and a second capacitor conductor each extending from the first outer surface of the silicon semiconductor structure into the silicon semiconductor structure in the thickness direction, and
a capacitor dielectric layer separating each of the first capacitor conductor and the second capacitor conductor from the silicon semiconductor structure.
14. The integrated circuit of claim 13 , further comprising a spacer dielectric layer separating the first capacitor conductor from the second capacitor conductor within the vertical gate.
15. The integrated circuit of claim 13 , further comprising driver circuitry configured to drive the vertical gate of the LDMOS transistor, wherein:
the driver circuitry is powered from a first power rail; and
the trench capacitor is electrically coupled across the first power rail.