Semiconductor device and manufacturing method thereof
A semiconductor device includes a substrate, a semiconductor channel layer, a gate electrode, and a first memory structure. The semiconductor channel layer is disposed on the substrate. The gate electrode and the first memory structure are disposed on the semiconductor channel layer. The first memory structure includes a first bottom plate, a first top plate, and a first memory element layer. The first top plate is disposed on the first bottom plate. The first memory element layer is disposed between the first bottom plate and the first top plate. The first bottom plate contacts the semiconductor channel layer. Purposes of process simplification and/or memory density enhancement may be achieved by integrating a transistor with a memory structure.
1. A semiconductor device, comprising:
a substrate;
a semiconductor channel layer disposed on the substrate;
a gate electrode disposed on the semiconductor channel layer;
a first memory structure disposed on the semiconductor channel layer, wherein the first memory structure comprises:
a first bottom plate;
a first top plate disposed on the first bottom plate; and
a first memory element layer disposed between the first bottom plate and the first top plate, wherein the first bottom plate contacts the semiconductor channel layer;
an interconnection structure disposed between the substrate and the semiconductor channel layer; and
a metal oxide semiconductor (MOS) structure disposed between the substrate and the interconnection structure.
2. The semiconductor device according to claim 1 , further comprising:
a gate dielectric layer disposed on the semiconductor channel layer and the first memory structure, wherein the gate electrode is disposed on the gate dielectric layer.
3. The semiconductor device according to claim 1 , wherein a part of the first top plate is disposed between the gate electrode and the semiconductor channel layer in a thickness direction of the substrate.
4. The semiconductor device according to claim 1 , wherein the first memory structure comprises a random access memory (RAM) structure, a resistive RAM (RRAM) structure, a phase change RAM (PCRAM) structure, a magnetoresistive RAM (MRAM) structure, or a ferroelectric RAM (FeRAM) structure.
5. The semiconductor device according to claim 1 , wherein the first memory element layer comprises a material with switchable resistance, a phase change material, a magnetic tunnel junction (MTJ) film stack, or a ferroelectric material.
6. The semiconductor device according to claim 1 , further comprising:
a source/drain electrode disposed on the semiconductor channel layer; and
a gate dielectric layer disposed on the semiconductor channel layer, the first memory structure, and the source/drain electrode, wherein the gate electrode, the gate dielectric layer, the semiconductor channel layer, the source/drain electrode, and the first bottom plate form a transistor.
7. The semiconductor device according to claim 1 , further comprising:
a second memory structure disposed on the semiconductor channel layer, wherein the first memory structure and the second memory structure are disposed at two opposite sides of the gate electrode respectively, and the second memory structure comprises:
a second bottom plate;
a second top plate disposed on the second bottom plate; and
a second memory element layer disposed between the second bottom plate and the second top plate, wherein the second bottom plate contacts the semiconductor channel layer.
8. The semiconductor device according to claim 7 , wherein a part of the second top plate is disposed between the gate electrode and the semiconductor channel layer in a thickness direction of the substrate.
9. The semiconductor device according to claim 7 , wherein the second memory structure comprises a random access memory (RAM) structure, a resistive RAM (RRAM) structure, a phase change RAM (PCRAM) structure, a magnetoresistive RAM (MRAM) structure, or a ferroelectric RAM (FeRAM) structure.
10. The semiconductor device according to claim 7 , further comprising:
a gate dielectric layer disposed on the semiconductor channel layer, the first memory structure, and the second memory structure, wherein the gate electrode, the gate dielectric layer, the semiconductor channel layer, the first bottom plate, and the second bottom plate form a transistor.
11. A manufacturing method of a semiconductor device, comprising:
forming a semiconductor channel layer on a substrate;
forming a gate electrode on the semiconductor channel layer; and
forming a first memory structure on the semiconductor channel layer, wherein the first memory structure comprises:
a first bottom plate;
a first top plate disposed on the first bottom plate; and
a first memory element layer disposed between the first bottom plate and the first top plate, wherein the first bottom plate contacts the semiconductor channel layer;
forming an interconnection structure, wherein the interconnection structure is located between the substrate and the semiconductor channel layer; and
forming a metal oxide semiconductor (MOS) structure, wherein the MOS structure is located between the substrate and the interconnection structure.
12. The manufacturing method of the semiconductor device according to claim 11 , further comprising:
forming a gate dielectric layer on the semiconductor channel layer and the first memory structure before the step of forming the gate electrode, wherein the gate electrode is formed on the gate dielectric layer.
13. The manufacturing method of the semiconductor device according to claim 11 , wherein a part of the first top plate is disposed between the gate electrode and the semiconductor channel layer in a thickness direction of the substrate.
14. The manufacturing method of the semiconductor device according to claim 11 , further comprising:
forming a source/drain electrode on the semiconductor channel layer, wherein the source/drain electrode and the first bottom plate are formed concurrently by the same process.
15. The manufacturing method of the semiconductor device according to claim 11 , further comprising:
forming a second memory structure on the semiconductor channel layer, wherein the first memory structure and the second memory structure are formed at two opposite sides of the gate electrode respectively, and the second memory structure comprises:
a second bottom plate;
a second top plate disposed on the second bottom plate; and
a second memory element layer disposed between the second bottom plate and the second top plate, wherein the second bottom plate contacts the semiconductor channel layer.
16. The manufacturing method of the semiconductor device according to claim 15 , wherein a part of the second top plate is disposed between the gate electrode and the semiconductor channel layer in a thickness direction of the substrate.
17. The manufacturing method of the semiconductor device according to claim 15 , further comprising:
forming a gate dielectric layer on the semiconductor channel layer, the first memory structure, and the second memory structure, wherein the gate electrode is formed on the gate dielectric layer.
18. The manufacturing method of the semiconductor device according to claim 15 , wherein the first memory structure and the second memory structure are formed concurrently by the same process.
19. The manufacturing method of the semiconductor device according to claim 18 , wherein the step of forming the first memory structure and the second memory structure comprises:
forming a first conductive layer on the semiconductor channel layer;
forming a memory element material on the first conductive layer;
forming a second conductive layer on the memory element material; and
patterning the second conductive layer, the memory element material, and the first conductive layer to form the first memory structure and the second memory structure.