IP Library Granted Patent US 11,079,963
Granted Patent B2
US 11,079,963 · App. 16/001,143 · Granted Aug 3, 2021

Storage device and communication control method

Inventor: Takuya Sekine (Kanagawa, JP)
Assignee: TOSHIBA MEMORY CORPORATION
G06F3/0659G06F3/0604G06F3/0625G06F3/0634G06F3/0635G06F3/0679G06F3/0688
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Quick Facts
Patent No.
US 11,079,963
App. No.
16/001,143
Granted
Aug 3, 2021
Kind
B2
Abstract

A storage device includes a nonvolatile memory and a controller. The controller is configured to control a first communication with a host device which is performed at a first transfer rate, and a second communication with the nonvolatile memory. The controller includes a detection circuit configured to detect a second transfer rate in the second communication with the nonvolatile memory, a processor configured to determine a target transfer rate in the first communication based on the second transfer rate detected by the detection circuit, and an interface configured to perform the first communication with the host device at the target transfer rate.

Claims (38)

1. A storage device comprising:

a nonvolatile memory; and

a controller configured to control a first communication with a host device, and a second communication with the nonvolatile memory, wherein the controller includes:

a detection circuit configured to detect a transfer rate in the second communication with the nonvolatile memory;

an interface circuit that is configurable to operate in one of a plurality of different operating modes to perform the first communication with the host device at a transfer rate corresponding to said one of the operating modes of the interface circuit; and

a processor configured to determine an operating mode of the interface circuit based on the transfer rate in the second communication, and set the interface circuit to operate in the determined operating mode.

2. The storage device according to claim 1 , wherein the detection circuit is configured to detect the transfer rate in the second communication based on the number of channels of the controller connected to the nonvolatile memory and a frequency used in the second communication.

3. The storage device according to claim 1 , wherein the detection circuit is configured to detect the transfer rate in the second communication based on a power throttling set value set to limit power consumption of the storage device.

4. The storage device according to claim 1 , wherein the detection circuit is configured to detect the transfer rate in the second communication based on a temperature throttling set value set to limit a temperature of the storage device.

5. The storage device according to claim 1 , wherein the detection circuit is configured to detect the second transfer rate in the second communication based on the bandwidth consumption amount of a background job executed by the controller for the nonvolatile memory.

6. The storage device according to claim 1 , wherein the detection circuit is configured to obtain the transfer rate in the second communication based on the bandwidth consumption rate of a background job executed by the controller for the nonvolatile memory.

7. The storage device according to claim 1 , wherein the interface circuit is configured with multiple link widths and multiple generations, and the processor sets the interface circuit to operate in the determined operating mode by changing a link width of the interface circuit and a generation of the interface circuit.

8. A storage device comprising:

a nonvolatile memory; and

a controller configured to control a first communication with a host device, and a second communication with the nonvolatile memory,

wherein the controller includes:

a detection circuit configured to detect a first transfer rate in the first communication with the host device;

an interface circuit that is configurable to operate in one of a plurality of different operating modes to perform the first communication with the host device at a transfer rate corresponding to said one of the operating modes of the interface circuit; and

a processor configured to determine an operating mode of the interface circuit based on the transfer rate in the first communication, and set the interface circuit to operate in the determined operating mode.

9. The storage device according to claim 8 , wherein the interface circuit is configured with multiple link widths and multiple generations, and the processor sets the interface circuit to operate in the determined operating mode by changing a link width of the interface circuit and a generation of the interface circuit.

10. The storage device according to claim 8 , wherein

the detection circuit detects the transfer rate in the first communication based on a performance throttling set value that is set to limit the performance of the storage device.

11. A communication control method comprising:

performing a first communication between a host device and a storage device including a nonvolatile memory and a controller that controls the nonvolatile memory;

detecting a transfer rate in a second communication between the controller and the nonvolatile memory;

determining an operating mode of an interface circuit of the controller based on the transfer rate in the second communication; and

configuring the interface circuit to operate in the determined operating mode to perform the first communication at a transfer rate corresponding to the determined operating mode.

12. The method according to claim 11 , further comprising:

detecting the transfer rate in the second communication and adjusting the transfer rate in the second communication based on the number of channels of the controller connected to the nonvolatile memory and a frequency used in the second communication.

13. The method according to claim 11 , further comprising:

detecting the transfer rate in the second communication and adjusting the transfer rate in the second communication based on a power throttling set value set to limit power consumption of the storage device.

14. The method according to claim 11 , further comprising:

detecting the transfer rate in the second communication and adjusting the transfer rate in the second communication based on a temperature throttling set value set to limit a temperature of the storage device.

15. The method according to claim 11 , further comprising:

detecting the transfer rate in the second communication and adjusting the transfer rate in the second communication based on the bandwidth consumption amount of a background job executed by the controller for the nonvolatile memory.

16. The method according to claim 11 , further comprising:

detecting the transfer rate in the second communication and adjusting the transfer rate in the second communication based on the bandwidth consumption rate of a background job executed by the controller for the nonvolatile memory.

17. The method according to claim 11 , wherein the interface circuit is configured by changing a link width of the interface circuit and a generation of the interface circuit.

Assignments (4)
CHANGE OF NAME AND ADDRESS Recorded Feb 4, 2022
From: K.K PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 058957/0124 →
CHANGE OF NAME AND ADDRESS Recorded Jan 31, 2022
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 058905/0582 →
MERGER Recorded Jan 31, 2022
From: TOSHIBA MEMORY CORPORATION
To: K.K PANGEA
Reel/Frame 058946/0675 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 6, 2018
From: SEKINE, TAKUYA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 045999/0203 →
Priority Claims (1)
JP JP2017-167155 · Aug 31, 2017 · national
Continuity (1)
Related Publication 20190065116A1 · Feb 28, 2019