Contact liner to enable different CPP devices

1. An apparatus comprising:

at least one first device that includes a first plurality of transistors, each transistor of the first plurality of transistors includes a gate with sidewall spacers adjacent to the gate, the at least one first device having a first contacted poly pitch (CPP) and a first contact in a first contact opening between the sidewall spacers of at least two transistor gates of the first plurality of transistors, the first contact having a first contact size; and

at least one second device that includes a second plurality of transistors, each transistor of the second plurality of transistors includes a gate with sidewall spacers adjacent to the gate, the at least one second device having a second CPP, a second contact opening between the sidewall spacers of at least two transistor gates of the second plurality of transistors, the second contact opening having sidewalls, a contact liner adjacent to the sidewalls of the second contact opening, a second contact in the second contact opening, the second contact having a second contact size, the second contact size constrained by the contact liner between the second contact and the sidewalls of the second contact opening;

wherein the second CPP is larger than the first CPP.

2. The apparatus of claim 1 , wherein the sidewall spacers of the first plurality of transistors have a first width, and the sidewall spacers of the second plurality of transistors have a second width, the first width being substantially equal to the second width.

3. The apparatus of claim 1 , wherein the first contact size is substantially equal to the second contact size.

4. The apparatus of claim 1 , wherein the contact liner has a thickness substantially equal to one-half of a difference between a length of the second CPP and a length of the first CPP.

5. The apparatus of claim 4 , wherein the thickness of the contact liner is at least 3 nm.

6. The apparatus of claim 1 , wherein the contact liner is comprised of a low-k dielectric material.

7. The apparatus of claim 6 , wherein the low-k dielectric material is selected from the group consisting of SiN, SiCN and SiBCN.

8. The apparatus of claim 1 , integrated into a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication system (PCS), a portable data unit, and/or a fixed location data unit.

9. A semiconductor die comprising:

a first plurality of transistors, each transistor of the first plurality of transistors includes a gate with sidewall spacers adjacent to the gate, the first plurality of transistors having a first contacted poly pitch (CPP), a first contact opening between the sidewall spacers of at least two transistor gates of the first plurality of transistors, the first contact opening having a first contact opening size; and

a second plurality of transistors, each transistor of the second plurality of transistors includes a gate with sidewall spacers adjacent to the gate, the second plurality of transistors having a second CPP that is larger than the first CPP, a second contact opening between the sidewall spacers of at least two transistor gates of the second plurality of transistors, the second contact opening having sidewalls, a contact liner adjacent to the sidewalls of the second contact opening, a second contact in the second contact opening, the second contact opening having a second contact opening size, the second contact opening size reduced by the contact liner between the second contact and the sidewalls of the second contact opening.

10. The semiconductor die of claim 9 , wherein the second contact opening size is substantially equal to the first contact opening size.