Test system having distributed resources
An example test system has resources that are distributed for access by a device under test (DUT). The example test system includes a device interface board (DIB) having sites to connect to devices to test, and a tester having slots configured to hold test instruments. Each test instrument has resources that are distributed over a dimension of the DIB. The resources are distributed to enable the devices in the sites equal access to the resources.
1. A system comprising:
a device interface board (DIB) comprising sites to connect to devices to test;
a tester comprising slots configured to hold test instruments, each test instrument having resources that are distributed over a dimension of the DIB, the resources being distributed to enable the devices in the sites equal access to the resources; and
an interconnect between the DIB and the tester, the interconnect comprising routing connections between the test instruments and the DIB;
wherein the interconnect comprises circuitry to process signals conducting through the routing connections; and
wherein the circuitry is configured to process the signals by combining first signals from two more routing connections to produce a second signal for output to a single routing connection, the single routing connection going to a resource on the DIB.
2. The system of claim 1 , wherein the dimension corresponds to an edge of the DIB and the resources are distributed across an entirety of the edge.
3. The system of claim 1 , wherein the dimension corresponds to an edge of the DIB and the resources are distributed symmetrically across multiple edges of the DIB.
4. The system of claim 1 , wherein the resources are distributed on the DIB so that the resources align, at least partly, to the sites.
5. The system of claim 1 , wherein the resources comprises electrical contacts enabling electrical pathways between the test instruments and the sites on the DIB.
6. The system of claim 5 , wherein the electrical pathways between a subject test instrument and multiple sites on the DIB have equal electrical path lengths.
7. The system of claim 5 , wherein the electrical pathways between the sites on the DIB and a subject test instrument have equal impedances.
8. The system of claim 5 , wherein each electrical pathway between a site on the DIB and a subject test instrument produces a same amount of signal degradation.
9. The system of claim 1 , wherein the sites are distributed to enable parallel testing of identical devices connected to the sites.
10. The system of claim 1 , wherein the DIB comprises a printed circuit board (PCB) comprised of a number of layers; and
wherein the number of layers is proportional to a number of the test instruments in the tester.
11. The system of claim 1 , wherein the test instruments comprise contacts at a first pitch and the resources are at a second pitch, the second pitch being less than the first pitch; and
wherein at least some of the routing connections are configured to go from the contacts of the test instruments at the first pitch to the resources at the second pitch.
12. The system of claim 1 , wherein the second signal has a higher bitrate than each of the first signals.
13. The system of claim 1 , wherein the resources comprise electrical contacts on the DIB.
14. The system of claim 1 , wherein each site on the DIB has a same configuration.
15. A system comprising:
a device interface board (DIB) comprising sites to connect to devices to test;
a tester comprising slots configured to hold test instruments, each slot corresponding to electrical contacts that are distributed across an entire edge of the DIB that interfaces to the tester, the electrical contacts being distributed so that at least some electrical pathways between a subject test instrument and identical devices in different sites have equal electrical path lengths; and
an interconnect between the tester and the DIB, the interconnect being configured to translate a pitch of contacts on the test instruments to a pitch of the electrical contacts on the DIB;
wherein the contacts are at a first pitch and the electrical contacts are at a second pitch, the second pitch being less than the first pitch;
wherein the interconnect comprises routing connections that are configured to go from the contacts of the test instruments at the first pitch to the electrical contacts at the second pitch;
wherein the interconnect comprises circuitry to process signals conducting through the routing connections; and
wherein the circuitry is configured to process the signals by combining first signals from two more routing connections to produce a second signal to be output to a single routing connection, the single routing connection going to an electrical contact on the DIB.
16. The system of claim 15 , wherein the second signal has a higher bitrate than each of the first signals.
17. The system of claim 15 , wherein the electrical contacts are distributed symmetrically across multiple edges of the DIB.
18. The system of claim 17 , wherein the electrical contacts are distributed on the DIB so that the electrical contacts align, at least partly, to the sites.
19. The system of claim 17 , wherein the electrical pathways between the sites on the DIB and the subject test instrument have equal impedances.
20. The system of claim 17 , wherein each electrical pathway between a site on the DIB and the subject test instrument produces a same amount of signal degradation.
21. The system of claim 15 , wherein the sites are distributed to enable parallel testing of identical devices connected to the sites.
22. The system of claim 15 , wherein the DIB comprises a printed circuit board (PCB) comprised of a number of layers; and
wherein the number of layers is proportional to a number of the test instruments in the tester.