Semiconductor device having biasing structure for self-isolating buried layer and method therefor

1. A semiconductor device structure, comprising:

a semiconductor substrate having a first major surface and an opposing second major surface, wherein the semiconductor substrate comprises:

a floating buried doped region of a first conductivity type;

a first doped region of a second conductivity type interposed between the floating buried doped region and the first major surface; and

a semiconductor region of the second conductivity type disposed between the floating buried doped region and the second major surface;

a trench isolation structure extending from the first major surface through the first doped region, extending through the floating buried doped region, and extending into the semiconductor region, wherein:

the floating buried doped region adjoins the trench isolation structure; and

the trench isolation structure defines a perimeter for an active region of the semiconductor device structure;

an insulated trench structure extending from the first major surface through the first doped region and terminating within the floating buried doped region, wherein:

the insulated trench structure is disposed within the perimeter of the trench isolation structure;

the insulated trench structure defines a first portion and a second portion of the active region; and

the floating buried doped region electrically couples the first portion and the second portion of the active region together;

a first semiconductor device disposed within a first portion of the first doped region and within the first portion of the active region; and

a second semiconductor device disposed in the second portion of the active region and comprising a second portion of the first doped region and the floating buried doped region, wherein the second semiconductor device is configured as a first bias semiconductor device adapted to set a potential of the floating buried doped region.

2. The structure of claim 1 , wherein:

the second portion of the active region is laterally bounded in a plan view by the trench isolation structure and the insulated trench structure.

3. The structure of claim 1 , wherein:

the trench isolation structure comprises a plurality of sides in a plan view;

the insulated trench structure is disposed to extend from a first side to an opposing second side of the trench isolation structure; and

the second portion of the active region is laterally bounded in the plan view by the insulated trench structure, the first side, the second side, and a third side extending between the first side and second side.

4. The structure of claim 1 , wherein:

the insulated trench structure is configured so as to dispose the second portion of the active region in a corner portion of the trench isolation structure in a plan view.

5. The structure of claim 1 , wherein:

the trench isolation structures defines a plurality of sides in a plan view;

the insulated trench structure comprises:

a first part extending between a first side to an opposing second side of the trench isolation structure; and

a second part extending between the first side to the opposing second side of the trench isolation structure;

the first part is laterally separated from the second part; and

the second portion of the active region is interposed between the first part and the second part.

6. The structure of claim 1 , wherein:

the insulated trench structure comprises a closed shape in a plan view; and

the insulated trench structure is disposed such that no portion of the insulated trench structure physically contacts the trench isolation structure.

7. The structure of claim 1 , wherein:

the insulating trench structure further defines a third portion of the active region;

the semiconductor device structure further comprises a third semiconductor device disposed in the third portion of active region;

the third semiconductor device comprising a third portion of the first doped region and the floating buried doped region;

the third semiconductor device is configured as a second bias semiconductor device adapted to set a potential of the floating buried doped region; and

the second semiconductor device and the third semiconductor device are in electrical communication through the floating buried doped region.

8. The structure of claim 7 , wherein the floating buried doped region has a varying dopant concentration.

9. The structure of claim 7 , wherein at least one of the second semiconductor device and the third semiconductor device comprises a bipolar transistor.

10. The structure of claim 1 , wherein the second semiconductor device further comprises:

a second doped region of the first conductivity type disposed within the second portion of first doped region and separated from the floating buried doped region by the first doped region; and

a third doped region of the second conductivity type disposed within the second doped region.

11. The structure of claim 1 , wherein:

the semiconductor device structure further comprises:

a first conductive electrode electrically coupled to the first semiconductor device adjacent the first major surface of the semiconductor substrate; and

a second conductive electrode electrically coupled to the second semiconductor device adjacent the first major surface of the semiconductor substrate;

the second semiconductor device further comprises a second doped region of the first conductivity type disposed within the second portion of the first doped region;

the second doped region is separated from the floating buried doped region by a portion of the first doped region; and

the second conductive electrode is adapted to electrically short the second doped region and the first portion of the first doped region together.

12. A semiconductor device structure, comprising:

a semiconductor substrate having a first major surface and an opposing second major surface, wherein the semiconductor substrate comprises:

a floating buried doped region of a first conductivity type;

a first doped region of a second conductivity type disposed between the floating buried doped region and the first major surface; and

a semiconductor region of the second conductivity type disposed between the floating buried doped region and the second major surface;

a trench isolation structure extending from the first major surface through the first doped region, extending through the floating buried doped region, and extending into the semiconductor region, wherein:

the floating buried doped region abuts the trench isolation structure; and

the trench isolation structure defines a perimeter for an active region of the semiconductor device structure;

an insulated trench structure extending from the first major surface through the first doped region and terminating within the floating buried doped region, wherein:

the insulated trench structure is disposed within the perimeter of the trench isolation structure;

the insulated trench structure defines a first portion, a second portion, and a third portion of the active region; and

the floating buried doped region electrically couples the first portion, the second portion, and the third portion of the active region together;

a first semiconductor device disposed within the first portion of the active region;

a first bias semiconductor device disposed within the second portion of the active region;

a second bias semiconductor device disposed within the third portion of the active region, wherein the first bias semiconductor device and the second bias semiconductor device are each adapted to set a potential of the floating buried doped region;

a first conductive electrode electrically coupled to the first semiconductor device;

a second conductive electrode electrically coupled to the first bias semiconductor device; and

a third conductive electrode electrically coupled to the second bias semiconductor device.

13. The structure of claim 12 , wherein the first portion of the active region is interposed between the second portion and the third portion of the active region.

14. The structure of claim 12 , wherein:

the insulated trench structure includes a portion that completely surrounds the second bias semiconductor device in a plan view; and

the portion that completely surrounds the second bias semiconductor device is laterally separated on all sides from the trench isolation structure in the plan view.

15. The structure of claim 12 , wherein the second bias semiconductor device comprises:

a second doped region of the first conductivity type disposed within the first doped region;

the second doped region is separated from the floating buried doped region by a portion of the first doped region; and

the third conductive electrode is coupled so as to electrically short the second doped region and the first doped region together.

16. The structure of claim 12 , wherein the floating buried doped region comprises:

a first region adjoining the first doped region;

a second region disposed between the first region and the semiconductor region, wherein the first region has a lower dopant concentration than the second region; and

a third region disposed between the second region and the semiconductor region, wherein the third region has a lower dopant concentration than the second region.

17. The structure of claim 16 , wherein at least a portion of the insulated trench structure terminates within the third region of the floating buried doped region.

18. The structure of claim 16 , wherein:

at least one of the first bias semiconductor device and the second bias semiconductor device comprises a diode; and

at least a portion of the insulated trench structure terminates within the second region of the floating buried doped region.

19. The structure of claim 12 , wherein the first conductive electrode, the second conductive electrode, and the third conductive electrode are each adapted to be independently biased.

20. A method of forming a semiconductor device comprising:

providing a semiconductor substrate having a first major surface and an opposing second major surface, wherein the semiconductor substrate comprises:

a floating buried doped region of a first conductivity type;

a first doped region of a second conductivity type disposed between the floating buried doped region and the first major surface; and

a semiconductor region of the second conductivity type disposed between the floating buried doped region and the second major surface;

providing a trench isolation structure extending from the first major surface through the first doped region, extending through the floating buried doped region, and extending into the semiconductor region, wherein:

the floating buried doped region adjoins the trench isolation structure; and

the trench isolation structure defines a perimeter for an active region of the semiconductor device structure;

providing an insulated trench structure extending from the first major surface through the first doped region and terminating within the floating buried doped region, wherein:

the insulated trench structure is disposed within the perimeter of the trench isolation structure;

the insulated trench structure defines a first portion, a second portion, and a third portion of the active region; and

the floating buried doped region electrically couples the first portion, the second portion, and the third portion of the active region together;

providing a first semiconductor device disposed within the first portion of the active region and within the first doped region;

providing a first bias semiconductor device disposed within the second portion of the active region and within the first doped region; and

providing a second bias semiconductor device disposed within the third portion of the active region and within the first doped region, wherein the first bias semiconductor device and the second bias semiconductor device are each adapted to set a set a potential of the floating buried doped region.