Semiconductor memory device
A semiconductor memory device according to an example embodiment of the present inventive concept may include: a plurality of lower electrodes located on a substrate and spaced apart from one another; and an etch stop pattern located on the substrate and surrounding at least a part of each of the plurality of lower electrodes, in which the etch stop pattern includes: a first etch stop pattern including carbon; and a second etch stop pattern located on the first etch stop pattern and including a material different from a material of the first etch stop pattern.
1. A semiconductor memory device comprising:
a plurality of lower electrodes located on a substrate and spaced apart from one another;
a first etch stop pattern located on the substrate and surrounding a lower portion of a sidewall of each of the plurality of lower electrodes; and
a second etch stop pattern located on the first etch stop pattern,
wherein a horizontal cross-sectional area of the second etch stop pattern decreases and then increases as the horizontal cross-sectional area of the second etch stop pattern goes away from the substrate in a vertical direction.
2. The semiconductor memory device of claim 1 , wherein a horizontal cross-sectional area of the first etch stop pattern varies in the vertical direction.
3. The semiconductor memory device of claim 1 , wherein a horizontal cross-sectional area of the first etch stop pattern decreases as the horizontal cross-sectional area of the first etch stop pattern goes away from the substrate in the vertical direction.
4. The semiconductor memory device of claim 1 , wherein a minimum horizontal cross-sectional area of the first etch stop pattern is greater than a maximum horizontal cross-sectional area of the second etch stop pattern.
5. The semiconductor memory device of claim 1 , wherein a vertical thickness of the first etch stop pattern is less than a vertical thickness of the second etch stop pattern.
6. The semiconductor memory device of claim 1 , wherein at least a part of a top surface of the first etch stop pattern contacts the plurality of lower electrodes.
7. A semiconductor memory device comprising:
a plurality of lower electrodes located on a substrate, spaced apart from one another and having a hollow column shape;
a first etch stop pattern located on the substrate and surrounding a lower portion of each of the plurality of lower electrodes; and
a second etch stop pattern located on the first etch stop pattern,
wherein each of the plurality of lower electrodes comprises:
a first portion arranged at a first level and defining a first inner space;
a second portion arranged at a second level higher than the first level and defining a second inner space; and
a third portion arranged at a third level higher than the second level and defining a third inner space,
wherein a horizontal width of the second inner space is greater than a horizontal width of the third inner space.
8. The semiconductor memory device of claim 7 , wherein a gradient of a cross-sectional profile of the third portion in a vertical direction is greater than a gradient of a cross-sectional profile of the first portion in the vertical direction.
9. The semiconductor memory device of claim 7 , wherein the first level is substantially the same as a level of the first etch stop pattern.
10. The semiconductor memory device of claim 7 , wherein the second level is substantially the same as a level of the second etch stop pattern.
11. The semiconductor memory device of claim 7 , wherein a horizontal cross-sectional area of the first portion decreases as the horizontal cross-sectional area of the first portion goes toward the substrate.
12. The semiconductor memory device of claim 11 , further comprising a conductive contact passing through at least a part of the substrate and connected to a bottom surface of the first portion,
wherein a width of a top surface of the conductive contact is substantially the same as a width of the bottom surface of the first portion.
13. The semiconductor memory device of claim 7 , wherein a horizontal cross-sectional area of the second portion increases and then decreases as the horizontal cross-sectional area of the second portion goes away from the substrate.
14. The semiconductor memory device of claim 7 , wherein a horizontal cross-sectional area of the third portion is substantially constant.
15. The semiconductor memory device of claim 7 , wherein a cross-sectional profile of each of the plurality of lower electrodes in a vertical direction has inflection points at a boundary between the first and second portions and a boundary between the second and third portions.
16. The semiconductor memory device of claim 7 , further comprising a dielectric layer conformably formed on the plurality of lower electrodes,
wherein the dielectric layer has outward protrusions at the second level.