Very low power microcontroller system
A microcontroller system includes a processing unit supporting at least one near or sub Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. A power control system uses power gates to power control at least the memory blocks. In some embodiments, a wake-up interrupt controller is connected to the power control system and a voltage regulator system is used to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. A plurality of clocks can be connected to define clock domains associated with separate power domains.
1. A microcontroller system comprising:
low threshold voltage transistors;
high threshold voltage transistors having a threshold voltage greater than the low threshold voltage transistors;
a processing core having low threshold voltage transistors and operable at a first voltage;
a first memory block having high threshold voltage transistors and operable at a second voltage higher than the first voltage;
a peripheral circuit operable at a third voltage; and
a power control module operable at a fourth voltage.
2. The microcontroller system of claim 1 , further comprising a second memory block operable at a voltage distinct from the second voltage.
3. The microcontroller system of claim 1 , wherein the first memory block is operable at an adjustable voltage depending on operational mode.
4. The microcontroller system of claim 1 , wherein the first memory block is operable at an adjustable voltage depending on temperature.
5. The microcontroller system of claim 1 , wherein the first memory block is operable at an adjustable voltage depending on stored process corner characteristics information.
6. The microcontroller system of claim 1 , wherein the first memory block further comprises an internal supply voltage control having a voltage converter and regulator.
7. The microcontroller system of claim 6 , wherein the internal supply voltage control includes at least one of a buck converter and a LDO.
8. The microcontroller system of claim 1 , further comprising a cache block having low threshold voltage transistors and operable at a fifth voltage greater than the second voltage.
9. The microcontroller system of claim 1 , wherein processing core and the first memory block are independently power gated by the power control module.
10. The microcontroller system of claim 1 , wherein the first memory block is an SRAM block having operational modes that include active mode and retention mode.
11. The microcontroller system of claim 1 , wherein the first memory block further comprises first and second SRAM blocks operable at distinct voltages, the voltage values being at least one of a predetermined value, a selected value, and a dynamically adjusted value.
12. The microcontroller system of claim 11 , wherein each of the first and second SRAM blocks has an internal supply voltage control and a local register for storing at least one voltage value.
13. The microcontroller system of claim 1 , wherein at least a portion of the processing core is operable at subthreshold or near-threshold voltages.
14. The microcontroller system of claim 1 , wherein at least some of the low threshold voltage transistors can be body biased.
15. The microcontroller system of claim 1 , wherein the peripheral circuit includes an always-on circuit.
16. A microcontroller system comprising:
a processing core in a first power domain supplied at a first voltage, and having at least some low Vt transistors;
a first memory block in a second power domain supplied at a second voltage, the memory block having at least some high Vt transistors and an internal supply voltage control having a voltage converter and regulator; and wherein
the processing core and the memory block are independently power gated by power control circuits controlled by a power control module.
17. The microcontroller system of claim 16 , further comprising a second memory block operable at a voltage distinct from the second voltage.
18. The microcontroller system of claim 16 , wherein the first memory block is operable at an adjustable voltage depending on operational mode.
19. The microcontroller system of claim 16 , wherein the first memory block is an SRAM block having operational modes that include active mode and retention mode.
20. The microcontroller system of claim 16 , wherein the first memory block further comprises first and second SRAM blocks operable at distinct voltages, the voltage values being at least one of a predetermined value, a selected value, and a dynamically adjusted value.
21. The microcontroller system of claim 20 , wherein each of the first and second SRAM blocks has a local register for storing at least one voltage value.
22. The microcontroller system of claim 16 , wherein at least a portion of the processing core is operable at subthreshold or near-threshold voltages.