Gate-all-around structure and manufacturing method for the same
Present disclosure provides gate-all-around structure including a semiconductor fin having a top surface, a first nanowire over the top surface, a first space between the top surface and the first nanowire, an N th nanowire and an (N+1) th nanowire over the first nanowire, and a second space between the N th nanowire and the (N+1) th nanowire. The first space is greater than the second space. Present disclosure also provides a method for manufacturing the gate-all-around structure described herein.
1. A gate-all-around structure, comprising:
a semiconductor fin having a top surface;
a first nanowire over the top surface;
a first space between the top surface and the first nanowire;
an N th nanowire and an (N+1) th nanowire over the first nanowire, N being an integer greater than 1;
a second space between the N th nanowire and the (N+1) th nanowire, wherein the first space is greater than the second space; and
a third space between the first nanowire and the N th nanowire, wherein the third space is greater than the second space.
2. The structure of claim 1 , wherein a thickness of the first nanowire is identical to a thickness of the N th and a thickness of the (N+1) th nanowire.
3. The structure of claim 1 , further comprising a gate filling the first space, the second space and the third space.
4. The structure of claim 1 , further comprising a source or a drain filling the first space, the second space and the third space.
5. The structure of claim 1 , wherein the first nanowire is composed of silicon.
6. The structure of claim 1 , further comprising:
an (N+2) th nanowire over the (N+1) th nanowire, wherein a fourth space is between the (N+1) th nanowire and the (N+2) th nanowire, and the second space is greater than the fourth space.
7. A semiconductor structure, comprising:
a P-type transistor, comprising:
a semiconductor fin having a top surface;
a first SiGe nanowire over the top surface of the semiconductor fin;
a second SiGe nanowire, an N th SiGe nanowire, and an (N+1) th SiGe nanowire over the first SiGe nanowire, N being an integer greater than 1;
a first space between the first SiGe nanowire and the second SiGe nanowire; and
a second space between the N th SiGe nanowire and the (N+1) th SiGe nanowire;
wherein the first space is greater than the second space.
8. The semiconductor structure of claim 7 , wherein a thickness of the first SiGe nanowire is identical to a thickness of the second SiGe nanowire, the N th SiGe nanowire, and the (N+1) th SiGe nanowire.
9. The semiconductor structure of claim 7 , wherein the first space is greater than the second space by a range of from about 0.5 nm to about 1.5 nm.
10. The semiconductor structure of claim 7 , further comprising a first gate filling the first space and the second space.
11. The semiconductor structure of claim 7 , further comprising a first source or a first drain filling the first space and the second space.
12. The semiconductor structure of claim 7 , further comprising:
an N-type transistor, comprising:
a first Si nanowire over the top surface of the semiconductor fin;
a third space between the top surface and the first Si nanowire;
an N th Si nanowire, and an (N+1) t Si nanowire over the first Si nanowire, N being an integer greater than 1; and
a fourth space between the N th Si nanowire and the (N+1) th Si nanowire;
wherein the third space is greater than the fourth space.
13. The semiconductor structure of claim 12 , wherein a thickness of the first Si nanowire is identical to a thickness of the N th Si nanowire and the (N+1) th Si nanowire.
14. The semiconductor structure of claim 12 , further comprising a second gate filling the third space and the fourth space.
15. The semiconductor structure of claim 12 , further comprising a second source or a second drain filling the third space and the fourth space.
16. A semiconductor structure, comprising:
a semiconductor fin having a top surface;
a first nanowire over the top surface;
an N th nanowire over the first nanowire, N being an integer greater than 1; and
an (N+1) th nanowire over the N th nanowire, wherein a thickness of the first nanowire is identical to a thickness of the N th nanowire, a first space is between the top surface of the semiconductor fin and the first nanowire, a second space is between the N th nanowire and the (N+1) th nanowire, the first space and the second space are filled with a doped material or a gate material; and
an (N+2) th nanowire over the (N+1) th nanowire, wherein a third space is between the (N+1) th nanowire and the (N+2) th nanowire, the second space being greater than the third space.
17. The semiconductor structure of claim 16 , wherein the first space is greater than the second space.
18. The semiconductor structure of claim 16 , wherein the first space is at least greater than the second space by a range of from about 0.5 nm to about 1.5 nm.
19. The semiconductor structure of claim 16 , wherein a concentration of germanium of the N th nanowire of the first transistor is in a range from 20% to 75%.
20. The semiconductor structure of claim 16 , wherein the third space is filled with the doped material or the gate material.