Stress induction in 3D device channel using elastic relaxation of high stress material
A method for inducing stress in a device channel includes forming a stress adjustment layer on a substrate, the stress adjustment layer including an as deposited stress due to crystal lattice differences with the substrate. A device channel layer is formed on the stress adjustment layer. Cuts are etched through the device channel layer and the stress adjustment layer to release the stress adjustment layer to induce stress in the device channel layer. Source/drain regions are formed adjacent to the device channel layer.
1. A method for inducing stress in a device channel, comprising:
forming a device channel layer on a strain adjustment layer including Si 3 P 4 , wherein the device channel layer includes alternating layers of channel layers and stress adjustment layers, and wherein the stress adjustment layers include same materials as the strain adjustment layer; and
etching fins into the device channel layer and the strain adjustment layer to release the strain adjustment layer to induce stress in the device channel layer.
2. The method as recited in claim 1 , wherein the strain adjustment layer includes a tensile stress to form a compressive stress in the device channel layer.
3. The method as recited in claim 1 , wherein the strain adjustment layer includes pseudocubic Si 3 P 4 .
4. The method as recited in claim 3 , wherein the device channel layer includes a material selected from the group consisting of silicon (Si) and silicon germanium (SiGe).
5. The method as recited in claim 1 , further including forming source/drain regions adjacent to the device channel layer includes forming stressed source/drain regions to externally provide additional stress to the device channel layer.
6. The method as recited in claim 1 , further including source/drain regions including boron doping.
7. The method as recited in claim 1 , wherein the device channel layer includes layers in a nanosheet.
8. A method for inducing stress in a device channel, comprising:
forming a strain adjustment layer including Si 3 P 4 on a substrate, the strain adjustment layer including an as deposited stress due to crystal lattice differences with the substrate;
forming a device channel layer on the strain adjustment layer, wherein the device channel layer includes alternating layers of channel layers and stress adjustment layers, and wherein the stress adjustment layers include same materials as the strain adjustment layer; and
forming fins in the device channel layer on the strain adjustment layer such that the strain adjustment layer is released to induce stress in the device channel layer.
9. The method as recited in claim 8 , wherein the strain adjustment layer includes a tensile stress to form a compressive stress in the device channel layer.
10. The method as recited in claim 8 , wherein the strain adjustment layer includes a pseudocubic Si 3 P 4 .
11. The method as recited in claim 10 , wherein the device channel layer includes a material selected from the group consisting of silicon (Si) and silicon germanium (SiGe).
12. The method as recited in claim 8 , further including forming source/drain regions adjacent to the device channel layer includes forming stressed source/drain regions to externally provide additional stress to the device channel layer.
13. The method as recited in claim 8 , wherein the device channel layer includes a multi-layered nanosheet including the alternating layers of channel layers and stress adjustment layers.
14. The method as recited in claim 13 , further comprising forming a protection layer along sidewalls of the fins before forming the source/drain regions.
15. The method as recited in claim 13 , further comprising:
recessing the alternating stress adjustment layers and the strain adjustment layer; and
depositing a dielectric material in the recesses to protect sidewalls of the fins before forming source/drain regions.
16. The method as recited in claim 13 , further comprising:
removing the alternating stress adjustment layers and the strain adjustment layer to form a void and to expose the alternating channel layers such that the alternating channel layers are clamped between source/drain regions to maintain stress; and
forming gate material to fill the void.
17. A semiconductor device having compressive stress in a device channel, comprising:
fins on a substrate, the fins including:
a Si 3 P 4 strain adjustment layer formed on the substrate; and
a device channel layer formed on the Si 3 P 4 strain stress adjustment layer, the device channel layer including a compressive stress induced by the Si 3 P 4 strain stress adjustment layer, wherein the device channel layer includes alternating layers of channel layers and stress adjustment layers, and wherein the stress adjustment layers include same materials as the Si 3 P 4 strain adjustment layer.
18. The device as recited in claim 17 , wherein the strain adjustment layer includes pseudocubic Si 3 P 4 and the device channel layer includes a material selected from the group consisting of silicon (Si) and silicon germanium (SiGe).
19. The device as recited in claim 17 , wherein source/drain regions externally provide additional stress to the device channel layer.
20. The method as recited in claim 17 , wherein the device channel layer includes a fin or layers in a nanosheet.