Vertical transistor with reduced parasitic capacitance
View Patent ↗A semiconductor structure includes a first fin and a second fin vertically disposed on a substrate. The first fin is adjacent to and parallel to the second fin. A first source/drain is disposed on the substrate, and a first dielectric spacer is disposed on the first source/drain. A gate is disposed on the first dielectric spacer and a portion of a vertical side of each of the first fin and the second fin. A trench is adjacent to and parallel to the first fin and the second fin. The trench extends through a portion of the substrate and includes a top portion being narrower than a bottom portion. A dielectric material is disposed within the trench and pinches off the top portion of the trench to form an air gap spacer within the trench. The air gap spacer is parallel to and between the first fin and the second fin.
1. An apparatus comprising:
a substrate;
a first fin and a second fin vertically disposed on the substrate, the first fin being adjacent to and parallel to the second fin;
a first source/drain disposed on the substrate;
a first dielectric spacer disposed on the first source/drain;
a gate disposed on the first dielectric spacer and a portion of a vertical side of each of the first fin and the second fin;
a trench adjacent to and parallel to the first fin and the second fin, the trench extending through a portion of the substrate, the trench including a top portion being narrower than a bottom portion;
a dielectric material disposed within the trench and pinching off the top portion of the trench to form an air gap spacer within the trench, the air gap spacer being parallel to and between the first fin and the second fin along a longitudinal axis; and
a first contact in contact with a second source/drain, the first contact partially overlying a portion of the air gap spacer along the longitudinal axis.
2. The apparatus of claim 1 , further comprising:
a second dielectric spacer on the gate, the gate being disposed between the first dielectric spacer and the second dielectric spacer.
3. The apparatus of claim 2 , wherein the second source/drain is disposed on the second dielectric spacer.
4. The apparatus of claim 1 , further comprising an interlayer dielectric deposited on the first fin, the second fin, and the substrate.
5. The apparatus of claim 4 , wherein the first contact is formed through the interlayer dielectric.
6. The apparatus of claim 4 , further comprising a second contact formed through the interlayer dielectric in contact with the gate.
7. The apparatus of claim 4 , further comprising a third contact formed through the interlayer dielectric in contact with the first source/drain.
8. The apparatus of claim 1 , wherein the air gap is confined between and parallel to the first fin and second fin.
9. The apparatus of claim 1 , wherein the air gap is not disposed at an end of the first fin and the second fin.