Gate activity analysis

1. A method for analyzing a processor design, the method comprising:

receiving, via a processing system, a design for a processor;

receiving, via the processing system, an application to be executed by the processor; and

simulating, via the processing system, the execution of the application on the processor for all possible executions of the application for any possible inputs to the application by performing symbolic simulation, where unknown input values are represented by symbolic values, based on the design to identify unexercisable gates of the processor,

wherein performing the symbolic simulation comprises:

initializing a list of unexercisable gates as all gates of a gate-level netlist of the design;

initializing all inputs to the simulation to Xs, where each X represents an unknown logic value;

simulating the application based on the gate-level netlist and an application binary for the application; and

removing each gate that toggles and each gate through which an X propagates during the simulation from the list of unexercisable gates, and

wherein performing the symbolic simulation further comprises:

tracking the most conservative gate-level state that has been observed for each conditional branch encountered during the simulation; and

in response to re-encountering a conditional branch while simulating on a control flow path;

terminating simulation down the control flow path in response to the symbolic state being simulated being a substate of the most conservative gate-level state previously observed at the conditional branch; and

in response to the symbolic state being simulated not being a substate of the most conservative gate-level state previously observed at the conditional branch, merging the symbolic state being simulated with the most conservative gate-level state previously observed at the conditional branch to an updated most conservative gate-level state for the conditional branch, and continuing simulation from the updated most conservative gate-level state.

2. The method of claim 1 , further comprising:

recording the constant values of each unexercisable gate.

3. A system comprising:

a machine readable storage medium storing instructions; and

a processor to execute the instructions to:

receive a gate-level netlist of a processor;

receive an application binary for an application to be executed by the processor; and

simulate the execution of the application on the processor for all possible executions of the application for any possible inputs to the application by performing symbolic simulation, where unknown input values are represented by symbolic values, based on the gate-level netlist and the application binary to identify unexercisable gates of the processor,

wherein the processor executes the instructions to perform the symbolic simulation to:

initialize a list of unexercisable gates as all gates of the gate-level netlist;

initialize all inputs to the simulation to Xs, where each X represents an unknown logic value;

simulate the application based on the gate-level netlist and the application binary; and

remove each gate that toggles and each gate through which an X propagates during the simulation from the list of unexercisable gates, and

wherein the processor executes the instructions to perform symbolic simulation to further;

track the most conservative gate-level state that has been observed for each conditional branch encountered during the simulation; and

in response to re-encountering a conditional branch while simulating on a control flow path;

terminate simulation down the control flow path in response to the symbolic state being simulated being a substate of the most conservative gate-level state previously observed at the conditional branch; and

in response to the symbolic state being simulated not being a substate of the most conservative gate-level state previously observed at the conditional branch, merge the symbolic state being simulated with the most conservative gate-level state previously observed at the conditional branch to create an updated most conservative gate-level state for the conditional branch, and continue simulation from the updated most conservative gate-level state.

4. The system of claim 3 , wherein the processor executes the instructions to further:

record the constant values of each unexercisable gate.

5. A method for analyzing a processor design, the method comprising:

receiving, via a processing system, a gate-level netlist of a processor;

receiving, via the processing system, an application binary for an application to be executed by the processor;

initializing a list of unexercisable gates as all gates of the gate-level netlist;

initializing all inputs to the simulation to Xs, where each X represents an unknown logic value;

simulating the application based on the gate-level netlist and the application binary;

removing each gate that toggles and each gate through which an X propagates during the simulation from the list of unexercisable gates;

tracking the most conservative gate-level state that has been observed for each conditional branch encountered during the simulation; and

in response to re-encountering a conditional branch while simulating on a control flow path:

terminating simulation down the control flow path in response to the symbolic state being simulated being a substate of the most conservative gate-level state previously observed at the conditional branch; and

in response to the symbolic state being simulated not being a substate of the most conservative gate-level state previously observed at the conditional branch, merging the symbolic state being simulated with the most conservative gate-level state previously observed at the conditional branch to create an updated most conservative gate-level state for the conditional branch, and continuing simulation from the updated most conservative gate-level state.

6. The method of claim 5 , further comprising:

recording the constant values of each unexercisable gate.