Vertical field effect transistor with reduced external resistance
A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a substrate and at least one semiconductor fin contacting the substrate. A first source/drain layer contacts the substrate. A silicide contacts and wraps around the first source/drain layer. The structure also includes a second source/drain layer above the first source/drain layer. The method comprises forming a structure including at least a substrate, a first source/drain layer, and at least one semiconductor fin disposed on and in contact with substrate. A silicide is formed in contact with and wrapping around the first source/drain layer. A gate structure is formed in contact with at least the at least one semiconductor fin. A second source/drain layer is formed above the first source/drain layer.
1. A method for forming a semiconductor structure, the method comprising at least:
forming a structure comprising at least a substrate, a first source/drain layer, and at least one semiconductor fin disposed on and in contact with substrate;
forming a silicide in contact with and wrapping around the first source/drain layer;
forming a gate structure in contact with at least the at least one semiconductor fin; and
forming a second source/drain layer above the first source/drain layer.
2. The method of claim 1 , further comprising:
forming a protective layer in contact with sidewalls of the at least one semiconductor fin prior to forming the silicide; and
removing at least a portion of the protective layer after the silicide has been formed.
3. The method of claim 1 , further comprising:
forming a spacer layer in contact with at least the silicide and the at least one semiconductor fin.
4. The method of claim 3 , further comprising:
forming the spacer layer in contact with a top surface of the substrate.
5. The method of claim 3 , further comprising:
forming an additional spacer layer in contact with the gate structure and the at least one semiconductor fin.
6. The method of claim 1 , wherein forming the second source/drain layer comprises:
forming the second source/drain layer in contact with the gate structure and the at least one semiconductor fin.
7. The method of claim 1 , further comprising:
forming a metal contact in contact with a contact area of the gate structure.
8. The method of claim 1 , further comprising:
forming a metal contact in contact with the second source/drain layer.
9. The method of claim 1 , further comprising:
forming a metal contact in contact with the silicide.
10. A semiconductor structure comprising at least:
a substrate;
at least one semiconductor fin contacting the substrate;
a first source/drain layer contacting the substrate;
a silicide contacting and wrapping around the first source/drain layer; and
a second source/drain layer above the first source/drain layer.
11. The semiconductor structure of claim 10 , further comprising:
a spacer layer contacting at least the silicide and the at least one semiconductor fin.
12. The semiconductor structure of claim 11 , wherein the spacer layer further contacts a top surface of the substrate.
13. The semiconductor structure of claim 11 , further comprising:
a gate structure contact the at least one semiconductor fin; and
an additional spacer layer formed above the spacer layer, wherein the additional spacer layer contacts the gate structure and the at least one semiconductor fin.
14. The semiconductor structure of claim 10 , wherein the second source/drain layer contacts the at least one semiconductor fin.
15. The semiconductor structure of claim 10 , wherein the second source/drain layer comprises a faceted portion.
16. An integrated circuit comprising:
one or more semiconductor devices, wherein at least one of the one or more semiconductor devices comprises at least:
a substrate;
at least one semiconductor fin contacting the substrate;
a first source/drain layer contacting the substrate;
a silicide contacting and wrapping around the first source/drain layer; and
a second source/drain layer above the first source/drain layer.
17. The integrated circuit of claim 16 , wherein the at least one of the one or more semiconductor devices further comprises:
a spacer layer contacting at least the silicide and the at least one semiconductor fin.
18. The integrated circuit of claim 17 , wherein the at least one of the one or more semiconductor devices further comprises:
a gate structure contact the at least one semiconductor fin; and
an additional spacer layer formed above the spacer layer, wherein the additional spacer layer contacts the gate structure and the at least one semiconductor fin.
19. The integrated circuit of claim 16 , wherein the second source/drain layer contacts the at least one semiconductor fin.
20. The integrated circuit of claim 16 , wherein the second source/drain layer comprises a faceted portion.