Self-aligned 3D memory with confined cell
A plurality of memory cells in a cross-point array in which the memory cell stacks in the cross-points include a switch element, a conductive barrier layer, and a memory cell in series, and having sides aligned within the cross-point area of the corresponding cross-point. The memory cells in the stacks include confinement spacers within the cross-point area having outside surfaces on a pair of opposing sides of the stack, and a body of programmable resistance memory material confined between inside surfaces of the spacers.
1. A memory, comprising:
a plurality of first conductors in a first conductor layer having sidewalls extending in a first direction, and a plurality of second conductors in a second conductor layer having sidewalls extending in a second direction and crossing over the plurality of first conductors at cross-points having cross-point areas defined by widths of the first and second conductors;
an array of memory cell stacks disposed in the cross-points between the first conductors and the second conductors, each memory cell stack in a corresponding cross-point in the array comprising:
a switch element, a conductive barrier layer, and a memory cell in series, and having sides aligned within the cross-point area of the corresponding cross-point, the memory cell including confinement spacers within the cross-point area having outside surfaces on a pair of opposing sides of the stack, and a body of programmable resistance memory material confined between inside surfaces of the spacers; and
a layer of the programmable resistance memory material lining the second conductors in the plurality of second conductors, and in contact with the bodies of programmable resistance memory material in the memory cell stacks, and separating the bodies of programmable resistance memory material from the second conductors at the corresponding cross-point.
2. The memory of claim 1 , wherein each memory cell stack includes a layer of confinement material having outside surfaces on a second pair of opposing sides of the stack within the cross-point area at the corresponding cross-point.
3. The memory of claim 2 , wherein the confinement spacers comprise silicon nitride, and the layer of confinement material comprises silicon nitride.
4. The memory of claim 1 , the programmable resistance memory material comprising a phase change material.
5. The memory of claim 1 , wherein the switch element comprises an ovonic threshold switch.
6. The memory of claim 1 , the programmable resistance memory material comprising a phase change material, and the switch element comprising an ovonic threshold switch.
7. The memory of claim 1 , wherein the confinement spacers comprise silicon nitride.
8. The memory of claim 1 , including:
a plurality of third conductors in a third conductor layer having sidewalls extending in the first direction, and over the plurality of second conductors at cross-points; and
an array of memory cell stacks disposed in the cross-points between the second conductors and the third conductors.
9. A memory, comprising:
a plurality of first conductors in a first conductor layer having sidewalls extending in a first direction, and a plurality of second conductors in a second conductor layer having sidewalls extending in a second direction and crossing over the plurality of first conductors at cross-points; and
an array of memory cell stacks disposed in the cross-points between the first conductors and the second conductors, each memory cell stack in a corresponding cross-point in the array comprising:
an ovonic threshold switch, a conductive barrier layer, and a memory cell in series, and having a first pair of opposing sides aligned with the sidewalls of the first conductor at the corresponding cross-point, and a layer of insulating material on a second pair of opposing sides aligned with the sidewalls of the second conductor at the corresponding cross-point, the memory cell including insulating spacers on the first pair of opposing sides and a body of phase change memory material confined between the spacers, the spacers having outside surfaces aligned with sidewalls of the first conductor at the corresponding cross-point; and
a layer of the phase change memory material lining the second conductors in the plurality of second conductors, and in contact with the bodies of phase change memory material in the memory cell stacks, and separating the bodies of phase change memory material from the second conductors at the corresponding cross-point.
10. The memory of claim 9 , wherein the insulating spacers comprise silicon nitride.
11. The memory of claim 9 , wherein the insulating spacers comprise silicon nitride, and the layer of insulating material comprises silicon nitride.
12. The memory of claim 9 , including:
a plurality of third conductors in a third conductor layer having sidewalls extending in the first direction, and over the plurality of second conductors at cross-points; and
a second array of memory cell stacks disposed in the cross-points between the second conductors and the third conductors.
13. A method of manufacturing an integrated circuit, comprising:
forming a plurality of first conductors in a first conductor layer having sidewalls extending in a first direction, and a plurality of second conductors in a second conductor layer having sidewalls extending in a second direction and crossing over the plurality of first conductors at cross-points having cross-point areas defined by widths of the first and second conductors; and
forming an array of memory cell stacks disposed in the cross-points between the first conductors and the second conductors, each memory cell stack in a corresponding cross-point in the array comprising:
a switch element, a conductive barrier layer, and a memory cell in series, and having sides aligned within the cross-point area of the corresponding cross-point, the memory cell including confinement spacers within the cross-point area having outside surfaces on a pair of opposing sides of the stack, and a body of programmable resistance memory material confined between inside surfaces of the spacers; and
forming a layer of the programmable resistance memory material lining the second conductors in the plurality of second conductors, and in contact with the bodies of programmable resistance memory material in the memory cell stacks, and separating the bodies of programmable resistance memory material from the second conductors at the corresponding cross-point.
14. The method of claim 13 , including:
forming a plurality of third conductors in a third conductor layer having sidewalls extending in the first direction, and over the plurality of second conductors at cross-points; and
forming a second array of memory cell stacks disposed in the cross-points between the second conductors and the third conductors.
15. The method of claim 13 , wherein forming the plurality of first conductors, the plurality of second conductors and the memory cell stacks, comprises:
forming a first stack of materials, including a layer of materials of the first conductors, a layer of materials of the switch element, a layer of materials of the conductive barrier and a sacrificial layer;
etching first trenches through the first stack to a level below the layer of materials of the first conductors in a pattern defining the sidewalls of the plurality of first conductors;
forming an insulating fill in the first trenches to a level coplanar with an upper surface of the sacrificial layer;
removing the sacrificial layer to form a plurality of second trenches aligned with sidewalls of the plurality of first conductors, and exposing the layer of materials of the conductive barrier;
forming insulating spacers on opposing sides of the second trenches to provide more narrow trenches within the plurality of second trenches;
depositing programmable resistance memory material in the more narrow trenches;
forming a layer of materials of the second conductors to provide a second stack; and
etching third trenches through the second stack to a level below the layer of materials of the switch element in a pattern to define the plurality of second conductors, and the opposing sides of the memory cells stacks aligned with the sidewalls of the second conductors.
16. The method of claim 15 , including:
before etching the third trenches, forming a second layer of materials of the first conductors, a second layer of materials of the switch element, a second layer of materials of the conductive barrier and a second sacrificial layer;
etching the third trenches;
forming an insulating fill in the third trenches to a level coplanar with an upper surface of the second sacrificial layer;
removing the second sacrificial layer to form a plurality of fourth trenches aligned with sidewalls of the plurality of second conductors, and exposing the second layer of materials of the conductive barrier;
forming second insulating spacers on opposing sides of the fourth trenches to provide second more narrow trenches within the plurality of fourth trenches;
depositing programmable resistance memory material in the second more narrow trenches;
forming a layer of materials of third conductors to provide a third stack; and
etching fifth trenches through the third stack to a level below the second layer of materials of the switch element in a pattern to define a plurality of third conductors, and opposing sides of a second array of memory cell stacks aligned with the sidewalls of the third conductors.
17. The method of claim 15 , including forming an insulating liner in the first trenches.
18. The method of claim 15 , wherein depositing programmable resistance memory material in the more narrow trenches, includes forming the layer of the programmable resistance material beneath the layer of materials of the second conductors.
19. The method of claim 13 , the programmable resistance memory material comprising a phase change material.
20. The method of claim 13 , wherein the switch comprises an ovonic threshold switch.