Gaseous spacer and methods of forming same
View Patent ↗A method for forming a gaseous spacer in a semiconductor device and a semiconductor device including the gaseous spacer are disclosed. In an embodiment, the method may include forming a gate stack over a substrate, depositing a first gate spacer on sidewalls of the gate stack, epitaxially growing source/drain regions on opposite sides of the gate stack, and depositing a second gate spacer over the first gate spacer to form a gaseous spacer below the second gate spacer. The gaseous spacer may be disposed laterally between the source/drain regions and the gate stack.
1. A method comprising:
forming a gate stack over a substrate;
depositing a first gate spacer on sidewalls of the gate stack;
epitaxially growing source/drain regions on opposite sides of the gate stack;
depositing a second gate spacer over the first gate spacer to form a gaseous spacer below the second gate spacer, the gaseous spacer being disposed laterally between the source/drain regions and the gate stack; and
after depositing the second gate spacer, planarizing the first gate spacer and the gate stack such that top surfaces of the first gate spacer and the gate stack are level with one another.
2. The method of claim 1 , wherein the gaseous spacer has a thickness of between 2 nm and 10 nm.
3. The method of claim 1 , wherein depositing the second gate spacer comprises depositing a second gate spacer material having a step coverage of less than 70 percent.
4. The method of claim 1 , wherein the gaseous spacer is disposed between the first gate spacer and the second gate spacer.
5. The method of claim 1 , wherein an upper boundary of the gaseous spacer is defined by a lower surface of the second gate spacer, the upper boundary of the gaseous spacer having a concave shape.
6. The method of claim 1 , further comprising forming a recess laterally between the source/drain regions and the gate stack, wherein the gaseous spacer is disposed in the recess.
7. A method comprising:
forming a gate stack over a semiconductor substrate;
forming a first gate spacer on sidewalls of the gate stack;
forming a dummy gate spacer over the first gate spacer;
forming epitaxial source/drain regions on opposite sides of the gate stack adjacent the dummy gate spacer;
etching the dummy gate spacer to form a recess between the epitaxial source/drain regions and the gate stack, the recess exposing top surfaces and sidewalls of the first gate spacer; and
forming a second gate spacer over the recess, wherein forming the second gate spacer forms a gas spacer in the recess.
8. The method of claim 7 , wherein the second gate spacer is formed after etching the dummy gate spacer.
9. The method of claim 7 , wherein an upper boundary of the gas spacer is defined by a bottom surface of the second gate spacer, the upper boundary of the gas spacer having a concave shape.
10. The method of claim 9 , wherein at least a portion of the upper boundary of the gas spacer is disposed below upper surfaces of the epitaxial source/drain regions.
11. The method of claim 7 , wherein at least a portion of the dummy gate spacer remains after etching the dummy gate spacer, and wherein the portion of the dummy gate spacer partially defines a boundary of the gas spacer.
12. The method of claim 7 , wherein a first epitaxial source/drain region and a second epitaxial source/drain region are formed on the same side of the gate stack, wherein the first epitaxial source/drain region is merged with the second epitaxial source/drain region, and wherein the gas spacer extends between the first epitaxial source/drain region and the second epitaxial source/drain region.
13. The method of claim 7 , wherein the recess has a width of between 5 nm and 7 nm.
14. The method of claim 7 , wherein forming the dummy gate spacer comprises:
depositing a dummy gate spacer layer, the dummy gate spacer layer having a thickness of between 6 nm and 7.5 nm; and
etching the dummy gate spacer layer to form the dummy gate spacer.
15. A semiconductor device comprising:
a gate stack over a semiconductor substrate;
a first gate spacer disposed on sidewalls of the gate stack;
a second gate spacer disposed on sidewalls of the first gate spacer, an uppermost surface of the second gate spacer being level with an uppermost surface of the first gate spacer;
an epitaxial source/drain region in the semiconductor substrate; and
a gas spacer disposed below the second gate spacer.
16. The semiconductor device of claim 15 , wherein the gas spacer is disposed between the epitaxial source/drain region and the gate stack.
17. The semiconductor device of claim 15 , wherein the gas spacer is disposed vertically between the first gate spacer and the second gate spacer, and wherein the gas spacer is disposed laterally between the epitaxial source/drain region and the first gate spacer.
18. The semiconductor device of claim 15 , wherein the gas spacer has a thickness of between 2 nm and 10 nm.
19. The semiconductor device of claim 15 , wherein the gas spacer has a width of between 5 nm and 7 nm.
20. The semiconductor device of claim 15 , wherein a top boundary of the gas spacer is defined by the second gate spacer, a first side boundary of the gas spacer is defined by the epitaxial source/drain region, a second side boundary of the gas spacer opposite the first side boundary is defined by the first gate spacer, and a bottom boundary of the gas spacer is defined by the first gate spacer.