Auto-tuning current limiter
View Patent ↗A power conversion circuit is provided. A reference signal is integrated over a first timer period. A second signal is generated that is approximately proportional to an output current of the power conversion circuit. The second signal is integrated over a second time period. A first result of the integration of the reference signal is compared to a second result of the integration of the second signal. A fault signal is asserted if the second result is greater than the first result.
1. A controller in a power conversion circuit, comprising:
an integration node coupled to an input of the controller;
a first amplifier including a first input coupled to the integration node, a second input coupled to a first reference source, and an output coupled to an output of the controller;
a capacitor coupled between the output of the first amplifier and the first input of the first amplifier;
a first switching circuit coupled between the input of the controller and the integration node;
a second switching circuit coupled between the integration node and a second reference source;
a counter including a first input coupled to the output of the first amplifier; and
a latching circuit including a first input coupled to an output of the counter, wherein the counter is configured to:
monitor a number of over-current conditions over time;
determine the number of over-current conditions exceeds a threshold amount; and in response,
assert a reset signal of the latching circuit.
2. The controller of claim 1 , further including:
a third switching circuit coupled between the output of the first amplifier and the first input of the first amplifier; and
a pulse generating circuit including an output coupled to a control input of the third switching circuit.
3. The controller of claim 1 , further including a second amplifier including a first input coupled to the output of the first amplifier, a second input coupled to the first reference source, and an output coupled to the output of the controller.
4. The controller of claim 1 , further including a second latching circuit including an output coupled to a control input of the first switching circuit.
5. The controller of claim 1 , wherein a control input of the second switching circuit is coupled to the output of the controller.
6. The controller of claim 1 , further including:
a filter including an input coupled to the input of the controller; and
a level shift circuit including an input coupled to an output of the filter and an output coupled to the integration node.
7. A controller in a power conversion circuit, comprising:
an integration node;
a first amplifier including a first input coupled to the integration node, a second input coupled to a first reference source, and an output coupled to an output of the controller;
a capacitor coupled between the output of the first amplifier and the first input of the first amplifier;
a first switching circuit coupled between the output of the first amplifier and the first input of the first amplifiers;
a counter including a first input coupled to the output of the first amplifier; and
a latching circuit including a first input coupled to an output of the counter, wherein the counter is configured to:
monitor a number of over-current conditions over time;
determine the number of over-current conditions exceeds a threshold amount; and in response,
assert a reset signal of the latching circuit.
8. The controller of claim 7 , further including a pulse generating circuit including an output coupled to a control input of the first switching circuit.
9. The controller of claim 7 , further including a second amplifier including a first input coupled to the output of the first amplifier, a second input coupled to the first reference source, and an output coupled to the output of the controller.
10. The controller of claim 7 , further including:
a second switching circuit coupled between an input of the controller and the integration node; and
a third switching circuit coupled between the integration node and a second reference source.
11. The controller of claim 10 , further including a second latching circuit including an output coupled to a control input of the second switching circuit.
12. The controller of claim 10 , wherein a control input of the third switching circuit is coupled to the output of the controller.
13. The controller of claim 7 , further including:
a filter including an input coupled to an input of the controller; and
a level shift circuit including an input coupled to an output of the filter and an output coupled to the integration node.
14. A controller in a power conversion circuit, comprising:
an integration node;
an integration circuit coupled to the integration node;
a first switching circuit coupled between an input of the controller and the integration node; and
a second switching circuit coupled between the integration node and a first reference source;
a counter including a first input coupled to an output of the integration circuit; and
a latching circuit including a first input coupled to an output of the counter, wherein the counter is configured to:
monitor a number of over-current conditions over time;
determine the number of over-current conditions exceeds a threshold amount; and in response,
assert a reset signal of the latching circuit.
15. The controller of claim 14 , wherein the integration circuit includes:
a first amplifier including a first input coupled to the integration node, a second input coupled to a second reference source, and an output coupled to an output of the controller;
a capacitor coupled between the output of the first amplifier and the first input of the first amplifier; and
a third switching circuit coupled between the output of the first amplifier and the first input of the first amplifier.
16. The controller of claim 15 , further including a pulse generating circuit including an output coupled to a control input of the third switching circuit.
17. The controller of claim 15 , further including a second amplifier including a first input coupled to the output of the first amplifier, a second input coupled to the second reference source, and an output coupled to the output of the controller.
18. The controller of claim 14 , further including a second latching circuit including an output coupled to a control input of the first switching circuit.
19. The controller of claim 14 , wherein a control input of the second switching circuit is coupled to the output of the controller.
20. The controller of claim 14 , further including:
a filter including an input coupled to an input of the controller; and
a level shift circuit including an input coupled to an output of the filter and an output coupled to the integration node.