Threshold voltage defined switches for programmable camouflage gates
Disclosed are various embodiments providing circuitry that includes camouflaged gates that each have multiple switches arranged in a predefined format. A switch at a specific position in one camouflaged gate can have a different threshold voltage than a switch at the specific position in another camouflaged gate. The logical function performed by the camouflaged gate can be based on which of the switches have a low threshold voltage and which of the switches have a high threshold voltage.
1. A circuit comprising:
a plurality of camouflaged gates, individual ones of the plurality of camouflaged gates comprising a respective plurality of switches arranged in a predefined format;
a first switch doped to have a threshold voltage at a first level, the first switch being one of the plurality of respective switches from a first camouflaged gate of the plurality of camouflaged gates, the first switch being arranged at a first location within the predefined format; and
a second switch doped to have the threshold voltage at a second level, the second switch being of the respective plurality of switches from a second camouflaged gate of the plurality of camouflaged gates, the second switch being arranged at the first location within the predefined format.
2. The circuit of claim 1 , wherein the first level is greater than the second level.
3. The circuit of claim 1 , wherein a count of each of the respective plurality of switches is one of: six or eight.
4. The circuit of claim 1 , wherein each of the plurality of camouflaged gates is one of: an AND gate, an OR gate, an XOR gate, a NAND gate, a NOR gate, or an XNOR gate.
5. The circuit of claim 1 , wherein a function corresponding to each of the plurality of camouflaged gates is based on which of the respective plurality of switches have a respective threshold voltage at the first level.
6. The circuit of claim 1 , wherein the first camouflaged gate and the second camouflaged gate are visually indistinguishable.
7. The circuit of claim 1 , wherein the first camouflaged gate and the second camouflaged gate differ only by which of the respective plurality of switches have the threshold voltage at the first level and which of the respective plurality of switches have the threshold voltage at the second level.
8. A circuit comprising:
a first switch of a first logic gate having a first threshold voltage, the first switch being located at a first location of a plurality of locations within a predefined arrangement;
a second switch of the first logic gate having a second threshold voltage, the second switch being located at a second location of the plurality of locations within the predefined arrangement; and
a third switch of a second logic gate having the second threshold voltage, the third switch being located at the first location of the plurality of locations within the predefined arrangement.
9. The circuit of claim 8 , further comprising a fourth switch of the second logic gate having the first threshold voltage, the fourth switch being located at the second location of the plurality of locations within the predefined arrangement.
10. The circuit of claim 8 , further comprising a plurality of logic gates including the first logic gate and the second logic gate, wherein each of the plurality of logic gates comprise eight switches with two of the switches being doped to have the second threshold voltage and six of the switches being doped to have the first threshold voltage.
11. The circuit of claim 8 , wherein the first logic gate and the second logic gate are visually indistinguishable.
12. The circuit of claim 8 , wherein the first gate and the second gate perform different logical functions.
13. The circuit of claim 8 , wherein the first threshold voltage and the second threshold voltage are substantially equidistance from an operating voltage.
14. A method comprising:
generating a first logic gate on a substrate, the first logic gate including a plurality of first switches arranged in a predefined format;
generating a second logic gate on the substrate, the second logic gate including a plurality of second switches arranged in the predefined format;
doping a first switch of the plurality of first switches to have a first threshold voltage, the first switch being at a first position of the predefined format; and
doping a second switch of the plurality of second switches to have a second threshold voltage, the second switch being at the first position of the predefined format.
15. The method of claim 14 , further comprising:
doping a third switch of the plurality of first switches to have the second threshold voltage, the third switch being at a second position of the predefined format; and
doping a fourth switch of the plurality of second switches to have the first threshold voltage, the fourth switch being at the second position of the predefined format.
16. The method of claim 14 , wherein the plurality of first switches comprises two switches doped to have the second threshold voltage and six switches doped to have the first threshold voltage, the first threshold voltage being greater than the second threshold voltage.
17. The method of claim 14 , further comprising optimizing a propagation delay for at least one of: the first logic gate or the second logic gate.
18. The method of claim 14 , further comprising optimizing a switching current for at least one of: the first logic gate or the second logic gate.
19. The method of claim 14 , wherein the first threshold voltage and the second threshold voltage are substantially equidistance from an operating voltage.
20. The method of claim 14 , wherein the first logic gate occupies a first area on the substrate and the second logic gate occupies a second area on the substrate, and the first area and second area are equal.