IP Library › Granted Patent US 11,869,973
Granted Patent B2
US 11,869,973 · App. 16/013,329 · Granted Jan 9, 2024

Nanowire transistor structure and method of shaping

Inventors: Erica J. Thompson (Beaverton, OR); Aditya Kasukurti (Hillsboro, OR); Jun Sung Kang (Portland, OR); Kai Loon Cheong (Beaverton, OR); Biswajeet Guha (Hillsboro, OR); William Hsu (Hillsboro, OR); Bruce Beattie (Portland, OR)
Assignee: Intel Corporation
H01L29/7853H01L29/0673H01L29/1037H01L29/1054H01L29/6653H01L29/6681H01L29/66818H01L29/7855H01L21/02238H01L21/02241H01L21/31111H01L21/31122H01L29/165H01L29/205H01L29/42392
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Quick Facts
Patent No.
US 11,869,973
App. No.
16/013,329
Granted
Jan 9, 2024
Kind
B2
Abstract

A nanowire device includes one or more nanowire having a first end portion, a second end portion, and a body portion between the first end portion and the second end portion. A first conductive structure is in contact with the first end portion and a second conductive structure is in contact with the second end portion. The body portion of the nanowire has a first cross-sectional shape and the first end portion has a second cross-sectional shape different from the first cross-sectional shape. Integrated circuits including the nanowire device and a method of cleaning a semiconductor structure are also disclosed.

Claims (27)

1. A semiconductor structure comprising:

a body comprising a semiconductor material;

a subfin beneath the body;

a gate structure wrapped around the body, and the gate structure on a top and along sidewalls of the subfin, the gate structure including a gate electrode and a gate dielectric between the body and the gate electrode, and the gate structure including a gate spacer; and

a source region and a drain region, the body being between the source and drain regions; wherein the body has a first cross-sectional shape under the gate dielectric and a second cross-sectional shape under the gate spacer, wherein the first cross-sectional shape is more rounded than the second cross-sectional shape, and wherein the gate spacer extends vertically beneath the second cross-sectional shape.

2. The semiconductor structure of claim 1 , wherein the body comprises a nanowire that has an external size defined by a minimum circumscribed circle and an internal size defined by a maximum inscribed circle, wherein the difference between the external size and the internal size is greater for the second cross-sectional shape than for the first cross-sectional shape.

3. The semiconductor structure of claim 1 , wherein the first cross-sectional shape has a first vertical height, the second cross-sectional shape has a second vertical height, and a ratio of the first vertical height to the second vertical height is no greater than 0.9.

4. The semiconductor structure of claim 1 , wherein the first cross-sectional shape has a first perimeter length, the second cross-sectional shape has a second perimeter length, and a ratio of the first perimeter length to the second perimeter length is no greater than 0.9.

5. The semiconductor structure of claim 1 , wherein the body is a first body, the structure further including one or more additional bodies, each of the first and additional bodies being a nanowire or nanoribbon, and each body having the first cross-sectional shape under the gate dielectric, wherein a perimeter length of the first cross-sectional shape differs by no more than 1.0 nm between any of the bodies.

6. The semiconductor structure of claim 5 , wherein the perimeter length of the first cross-sectional shape is less than 40 nm.

7. The semiconductor structure of claim 5 , wherein an average perimeter length of the first cross-sectional shape of the first and additional bodies has a standard deviation no greater than 1.0 nm.

8. The semiconductor structure of claim 7 , wherein the standard deviation is no greater than 0.5 nm.

9. The semiconductor structure of claim 1 , wherein the portion of the body having the second cross-sectional shape has a surface roughness that is greater than a surface roughness of the portion of the body having the first cross-sectional shape.

10. The semiconductor structure of claim 1 , wherein the portion of the body having the first cross-sectional shape consists essentially of silicon and the portion of the body having the second cross-sectional shape comprises silicon and germanium.

11. The semiconductor structure of claim of claim 1 , wherein the portion of the body having the first cross-sectional shape consists essentially of gallium and the portion of the body having the second cross-sectional shape comprises gallium and arsenic.

12. A nanowire transistor structure comprising:

a first region of semiconductor material;

a second region of semiconductor material;

one or more nanowires having a body between a first end portion in contact with the first region and a second end portion in contact with the second region;

a subfin beneath the body of the one or more nanowires; and

a gate structure around the body of the one or more nanowires, and the gate structure on a top and along sidewalls of the subfin, the gate structure comprising a gate electrode and a gate dielectric between the gate electrode and the body, and the gate structure including a gate spacer;

wherein the body of the one or more nanowires has a first cross-sectional shape and the first end portion has a second cross-sectional shape, wherein the first cross-sectional shape is more rounded than the second cross-sectional shape, and the first cross-sectional shape has a smaller circumference compared to the second cross-sectional shape, and wherein the gate spacer extends vertically beneath the second cross-sectional shape.

13. The nanowire transistor structure of claim 12 further comprising:

a source contact on the first region of semiconductor material; and

a drain contact on the second region of semiconductor material.

14. The nanowire transistor structure of claim 12 , wherein the gate structure is a first gate structure, and the nanowire transistor structure further comprising a second gate structure around the body and isolated from the first gate structure by a dielectric.

15. The nanowire device of claim 12 , wherein the one or more nanowires have an external size defined by a minimum circumscribed circle and an internal size defined by a maximum inscribed circle, wherein the difference between the external size and the internal size is greater for the second cross-sectional shape than for the first cross-sectional shape.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 21, 2018
From: BEATTIE, BRUCE; THOMPSON, ERICA J.; GUHA, BISWAJEET; KANG, JUN SUNG; KASUKURTI, ADITYA; CHEONG, KAI LOON; HSU, WILLIAM
To: INTEL CORPORATION
Reel/Frame 046154/0299 →
Continuity (1)
Related Publication 20190393350A1 · Dec 26, 2019