Content addressable memory device having electrically floating body transistor

1. A content addressable memory array comprising a plurality of content addressable memory cells arranged in a plurality of rows and columns, wherein each said content addressable memory cell comprises:

a first floating body transistor;

a second floating body transistor; and

a third transistor;

wherein said first floating body transistor and said second floating body transistor are electrically connected in series through a common node;

wherein said third transistor is electrically connected to said common node; and

wherein said first floating body transistor and said second floating body transistor store complementary data.

2. The content addressable memory array of claim 1 , wherein said first floating body transistor and said second floating body transistor comprise a buried well region.

3. The content addressable memory array of claim 1 , wherein said first floating body transistor and said second floating body transistor comprise a buried insulator region.

4. The content addressable memory array of claim 1 , wherein said first floating body transistor comprises a first gate region and said second floating body transistor comprises a second gate region.

5. The content addressable memory array of claim 1 , wherein said first floating body transistor comprises a first conductivity type and said third transistor comprises said first conductivity type.

6. The content addressable memory array of claim 1 , wherein said first floating body transistor comprises a first conductivity type and said third transistor comprises a second conductivity type different from said first conductivity type.

7. The content addressable memory array of claim 1 , wherein said third transistor comprises a third floating body transistor.

8. A content addressable memory array comprising a plurality of content addressable memory cells arranged in a plurality of rows and columns, wherein each said content addressable memory cell comprises:

a first bi-stable floating body transistor; and

a second bi-stable floating body transistor;

wherein said first bi-stable floating body transistor and said second bi-stable floating body transistor are electrically connected in series through a common node; and

wherein said first floating body transistor and said second floating body transistor store complementary data.

9. The content addressable memory array of claim 8 , wherein said first bi-stable floating body transistor and said second bi-stable floating body transistor comprise a buried well region.

10. The content addressable memory array of claim 8 , wherein said first bi-stable floating body transistor and said second bi-stable floating body transistor comprise a buried insulator region.

11. The content addressable memory array of claim 8 , wherein said first bi-stable floating body transistor comprises a first gate region and said second bi-stable floating body transistor comprises a second gate region.

12. The content addressable memory array of claim 8 , wherein each said content addressable memory cell further comprises an additional transistor.

13. The content addressable memory array of claim 12 , wherein said first bi-stable floating body comprises a first conductivity type and said additional transistor comprises said first conductivity type.

14. The content addressable memory array of claim 12 , wherein said first bi-stable floating body transistor comprises a first conductivity type and said additional transistor comprises a second conductivity type different from said first conductivity type.

15. The content addressable memory array of claim 8 , wherein each said content addressable memory cell further comprises a third bi-stable floating body transistor.

16. A content addressable memory array comprising a plurality of content addressable memory cells arranged in a plurality of rows and columns, wherein each said content addressable memory cell comprises:

a first transistor having a first floating body;

a second transistor having a second floating body;

a third transistor;

a first drain region contacting said first floating body;

a second drain region contacting said second floating body;

a first source region contacting said first floating body, spaced apart from said first drain region; and

a second source region contacting said second floating body, spaced apart from said second drain region;

wherein said first and second drain regions are electrically connected to each other;

wherein said third transistor is electrically connected to said first and second drain regions; and

wherein said first floating body and said second floating body store complementary charge states.

17. The content addressable memory array of claim 16 , wherein said first transistor and said second transistor comprise a buried well region.

18. The content addressable memory array of claim 16 , wherein said first transistor and said second transistor comprise a buried insulator region.

19. The content addressable memory array of claim 16 , wherein said first transistor comprises a first gate region and said second transistor comprises a second gate region.

20. The content addressable memory array of claim 16 , wherein said first transistor comprises a first conductivity type and said third transistor comprises said first conductivity type.

21. The content addressable memory array of claim 16 , wherein said first transistor comprises a first conductivity type and said third transistor comprises a second conductivity type different from said first conductivity type.

22. The content addressable memory array of claim 16 , further comprising a fourth transistor, having a third floating body.