Pixel control signal verification in a stacked image sensor
View Patent ↗An image sensor may be formed from stacked first and second substrates. An array of imaging pixels that each have a photodiode and accompanying transistors may be formed in the first substrate. Verification circuitry may also be formed in the first substrate. Row control circuitry may be formed in the second substrate. The row control circuitry may provide row control signals to the array of imaging pixels. The verification circuitry may also receive the row control signals from the row control circuitry. The first substrate may include a plurality of n-channel metal-oxide semiconductor transistors and may not include any p-channel metal-oxide semiconductor transistors. The second substrate may also include a p-channel metal-oxide semiconductor current source coupled to the verification circuitry. Only the verification circuitry portions that are enabled by control signals from the row control circuitry may receive current from the current source.
1. An image sensor comprising:
first and second substrates;
an array of imaging pixels in the first substrate, wherein each imaging pixel comprises a photodiode;
row control circuitry in the second substrate, wherein the row control circuitry is configured to provide row control signals to the array of imaging pixels; and
verification circuitry in the first substrate that receives the row control signals from the row control circuitry, wherein the first substrate includes a plurality of n-channel metal-oxide semiconductor transistors and does not include any p-channel metal-oxide semiconductor transistors.
2. The image sensor defined in claim 1 , further comprising:
a current source coupled to the verification circuitry.
3. The image sensor defined in claim 2 , wherein the current source is a p-channel metal-oxide semiconductor current source.
4. The image sensor defined in claim 3 , wherein the p-channel metal-oxide semiconductor current source is formed in the second substrate.
5. The image sensor defined in claim 2 , wherein the verification circuitry comprises a plurality of dummy pixels, wherein each dummy pixel has a respective verification circuitry portion, and wherein each dummy pixel receives a row select control signal from the row control circuitry that selectively enables the respective verification circuit portion for that dummy pixel.
6. The image sensor defined in claim 5 , wherein only the verification circuitry portions of dummy pixels that are enabled by the row select control signal receive current from the current source.
7. The image sensor defined in claim 5 , wherein each imaging pixel comprises a floating diffusion region, a transfer transistor coupled between the photodiode and the floating diffusion region, a source follower transistor coupled to the floating diffusion region, a reset transistor coupled to the floating diffusion region, and a row select transistor coupled to the source follower transistor.
8. The image sensor defined in claim 5 , wherein the plurality of dummy pixels includes at least one column of dummy pixels and wherein each column of dummy pixels in the at least one column of dummy pixels is coupled to a respective column output line.
9. The image sensor defined in claim 8 , wherein each column output line is coupled to a respective analog-to-digital converter.
10. An image sensor comprising:
first and second substrates;
an array of imaging pixels in the first substrate arranged in a plurality of rows and a plurality of columns;
a plurality of dummy pixels in the first substrate arranged in a plurality of rows and at least one column; and
row control circuitry in the second substrate, wherein the row control circuitry is configured to provide a respective control signal to each row of imaging pixels and each row of dummy pixels, wherein the control signal selectively enables verification circuitry in each dummy pixel, and wherein the first substrate does not include any p-channel metal-oxide semiconductor transistors.
11. The image sensor defined in claim 10 , further comprising:
a current source coupled to the verification circuitry in each dummy pixel in a first column of dummy pixels.
12. The image sensor defined in claim 11 , wherein the current source includes at least one p-channel metal-oxide semiconductor transistor.
13. The image sensor defined in claim 12 , wherein the current source is formed in the second substrate.
14. The image sensor defined in claim 13 , wherein only the verification circuitry that has been enabled by the control signal receives current from the current source.
15. The image sensor defined in claim 14 , wherein each imaging pixel comprises a floating diffusion region, a transfer transistor coupled between the photodiode and the floating diffusion region, a source follower transistor coupled to the floating diffusion region, a reset transistor coupled to the floating diffusion region, and a row select transistor coupled to the source follower transistor.
16. The image sensor defined in claim 15 , wherein a gate of the row select transistor of each imaging pixel receives the control signal from the row control circuitry.
17. An image sensor comprising:
a first substrate, wherein the first substrate comprises:
an array of imaging pixels that includes a plurality of n-channel metal-oxide semiconductor transistors and does not include any p-channel metal-oxide semiconductor transistors; and
verification circuitry that includes a plurality of n-channel metal-oxide semiconductor transistors and does not include any p-channel metal-oxide semiconductor transistors; and
a second substrate that is overlapped by the first substrate, wherein the second substrate comprises:
a current source coupled to the verification circuitry that includes at least one p-channel metal-oxide semiconductor transistor; and
row control circuitry in the second substrate, wherein the row control circuitry is configured to provide a first row control signal to a first row of imaging pixels in the array of imaging pixels and a first portion of the verification circuitry and wherein the first row control signal controls whether the first portion of the verification circuitry receives current from the current source.
18. The image sensor defined in claim 17 , wherein the first row control signal is provided to a gate of a row select transistor in each imaging pixel of the first row of imaging pixels.
19. The image sensor defined in claim 18 , wherein the row control circuitry is configured to provide a second row control signal to the first row of imaging pixels and the first portion of the verification circuitry and wherein the second row control signal is provided to a gate of a transfer transistor in each imaging pixel of the first row of imaging pixels.
20. The image sensor defined in claim 19 , wherein the row control circuitry is configured to provide a third row control signal to the first row of imaging pixels and the first portion of the verification circuitry and wherein the third row control signal is provided to a gate of a reset transistor in each imaging pixel of the first row of imaging pixels.