Work function based approaches to transistor threshold voltage tuning
A semiconductor device is disclosed. The semiconductor device includes a substrate, an epitaxial layer on the substrate, a semiconductor interlayer on top of the epitaxial layer, a gate conductor above the semiconductor interlayer, a gate insulator on the bottom and sides of the gate conductor and contacting the top surface of the semiconductor interlayer, a source region extending into the epitaxial layer, and a drain region extending into the epitaxial layer. The semiconductor device also includes a first polarization layer on the semiconductor interlayer between the source region and the gate conductor and a second polarization layer on the semiconductor interlayer between the drain region and the gate conductor.
1. A semiconductor device, comprising:
a substrate;
an epitaxial layer above the substrate, the epitaxial layer having a top surface;
a semiconductor interlayer above the epitaxial layer;
a gate conductor above the semiconductor interlayer;
a gate insulator on the bottom and sides of the gate conductor and contacting the top surface of the semiconductor interlayer;
an epitaxial source structure extending into the epitaxial layer, the epitaxial source structure having a bottom surface below the top surface of the epitaxial layer, and the epitaxial source structure having a top surface above the top surface of the epitaxial layer;
an epitaxial drain structure extending into the epitaxial layer, the epitaxial drain structure having a bottom surface below the top surface of the epitaxial layer, and the epitaxial drain structure having a top surface above the top surface of the epitaxial layer; and
a first polarization layer on the semiconductor interlayer between the epitaxial source structure and the gate conductor, and a second polarization layer on the semiconductor interlayer between the epitaxial drain structure and the gate conductor.
2. The semiconductor device of claim 1 , wherein the first polarization layer and the second polarization layer includes portions that extend respectively below a first spacer and a second spacer.
3. The semiconductor device of claim 1 , wherein the semiconductor device is an enhancement mode transistor.
4. The semiconductor device of claim 1 , wherein the semiconductor device is a depletion mode transistor.
5. The semiconductor device of claim 1 , wherein the epitaxial layer comprises GaN.
6. The semiconductor device of claim 1 , wherein the polarization layer is AlInGaN, AlInN, AlGaN or AlN.
7. The semiconductor device of claim 1 , wherein the epitaxial source structure and the epitaxial drain structure comprise n-type material.
8. A semiconductor device, comprising:
an enhancement mode transistor, comprising:
a first gate conductor above a first semiconductor interlayer, the first semiconductor interlayer above an epitaxial layer, the epitaxial layer having a top surface; and
a first polarization layer on the first semiconductor interlayer between a first epitaxial source structure and the first gate conductor, and a second polarization layer on the first semiconductor interlayer between an epitaxial drain structure and the first gate conductor, the first epitaxial source structure having a bottom surface below the top surface of the epitaxial layer, the first epitaxial source structure having a top surface above the top surface of the epitaxial layer, the epitaxial drain structure having a bottom surface below the top surface of the epitaxial layer, and the epitaxial drain structure having a top surface above the top surface of the epitaxial layer; and
a depletion mode transistor, comprising:
a second gate conductor above a second semiconductor interlayer, the second semiconductor interlayer above the epitaxial layer; and
a third polarization layer on the second semiconductor interlayer between a second epitaxial source structure and the second gate conductor, and a fourth polarization layer on the semiconductor interlayer between the epitaxial drain structure and the second gate conductor, the second epitaxial source structure having a bottom surface below the top surface of the epitaxial layer, and the second epitaxial source structure having a top surface above the top surface of the epitaxial layer.
9. The semiconductor device of claim 8 , wherein the first polarization layer, the second polarization layer, the third polarization layer and the fourth polarization layer extend respectively below a first spacer, a second spacer, a third spacer and a fourth spacer.
10. The semiconductor device of claim 8 , wherein the threshold voltage of the enhancement mode transistor is greater than zero.
11. The semiconductor device of claim 8 , wherein the threshold voltage of the depletion mode transistor is less than zero.
12. The semiconductor device of claim 8 , wherein the epitaxial layer comprises GaN.
13. The semiconductor device of claim 8 , wherein the polarization layer comprises AlInGaN, AlInN, AlGaN or AlN.
14. The semiconductor device of claim 8 , wherein the epitaxial source structure and the epitaxial drain structure comprise n-type material.
15. A method, comprising:
forming an epitaxial layer above a substrate, the epitaxial layer having a top surface;
forming a semiconductor interlayer above the epitaxial layer;
forming a gate conductor above the semiconductor interlayer;
forming a gate insulator on the bottom and sides of the gate conductor and contacting the top surface of the semiconductor interlayer;
forming an epitaxial source structure extending into the epitaxial layer, the epitaxial source structure having a bottom surface below the top surface of the epitaxial layer, and the epitaxial source structure having a top surface above the top surface of the epitaxial layer;
forming an epitaxial drain structure extending into the epitaxial layer, the epitaxial drain structure having a bottom surface below the top surface of the epitaxial layer, and the epitaxial drain structure having a top surface above the top surface of the epitaxial layer; and
forming a first polarization layer on the semiconductor interlayer between the source region and the gate conductor and a second polarization layer on the semiconductor interlayer between the drain region and the gate conductor.
16. The method of claim 15 , wherein the first polarization layer and the second polarization layer extend respectively below a first spacer and a second spacer.
17. The method of claim 15 , wherein the semiconductor device is an enhancement mode transistor.
18. The method of claim 15 , wherein the semiconductor device is a depletion mode transistor.
19. The method of claim 15 , wherein the epitaxial layer comprises GaN.
20. The method of claim 15 , wherein the polarization layer is AlInGaN, AlInN, AlGaN or AlN.