IP Library Granted Patent US 10,475,653
Granted Patent B2
US 10,475,653 · App. 16/016,602 · Granted Nov 12, 2019

Methods of fabricating ferroelectric memory devices

Inventor: Hyangkeun Yoo (Icheon-si, KR)
Assignee: SK hynix Inc.
H01L21/28291G11C11/2273G11C11/2275H01L21/0234H01L21/02181H01L21/02189H01L21/02304H01L21/02356H01L21/31155H01L27/1159H01L29/516H01L29/517H01L29/6684H01L29/78391G11C11/223
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Quick Facts
Patent No.
US 10,475,653
App. No.
16/016,602
Granted
Nov 12, 2019
Kind
B2
Abstract

A method of fabricating a ferroelectric memory device is provided. The method includes preparing a substrate, forming an interfacial insulation layer on the substrate, forming a ferroelectric layer on the interfacial insulation layer, applying a surface treatment process to the ferroelectric layer to form an oxygen vacancy region in the ferroelectric layer, forming a gate electrode layer on the ferroelectric layer, and annealing the ferroelectric layer to crystallize the ferroelectric layer.

Claims (47)

1. A method of fabricating a ferroelectric memory device, the method comprising:

preparing a substrate;

forming an interfacial insulation layer on the substrate;

forming a ferroelectric layer directly on the interfacial insulation layer;

applying a surface treatment process to the ferroelectric layer to form an oxygen vacancy region in the ferroelectric layer;

creating an electric field across the ferroelectric layer;

forming a gate electrode layer on the ferroelectric layer; and

annealing the ferroelectric layer to crystallize the ferroelectric layer,

wherein the oxygen vacancy region extends from a top surface of the ferroelectric layer into the bulk of the ferroelectric layer,

wherein the thickness of the oxygen vacancy region is one-half the thickness of the ferroelectric layer, and

wherein the oxygen vacancy region has a plurality of oxygen vacancies that act as positive charges.

2. The method of claim 1 , wherein the ferroelectric layer is formed to include a binary metal oxide material.

3. The method of claim 2 , wherein the ferroelectric layer is formed to include at least one of a hafnium oxide (HfO) material and a zirconium oxide (ZrO) material.

4. The method of claim 1 , wherein the surface treatment process includes a plasma process applied to the ferroelectric layer.

5. The method of claim 4 , wherein the plasma process is performed using an inert gas.

6. The method of claim 1 , wherein the surface treatment process includes injecting a dopant into an upper region of the ferroelectric layer.

7. The method of claim 6 ,

wherein the ferroelectric layer includes a binary metal oxide material and the dopant includes metal ions having a valence which is different from a valence of metal atoms in the binary metal oxide material.

8. The method of claim 7 , wherein the ferroelectric layer is formed to include a hafnium oxide (HfO) material or a zirconium oxide (ZrO) material, and the dopant includes at least one of carbon (C), silicon (Si), magnesium (Mg), aluminum (Al), yttrium (Y), germanium (Ge), tin (Sn), strontium (Sr), lead (Pb), calcium (Ca), barium (Ba), titanium (Ti), zirconium (Zr), gadolinium (Gd) and lanthanum (La).

9. The method of claim 1 ,

wherein the ferroelectric layer has a thickness of approximately seven (7) nanometers (nm) to approximately fifteen (15) nm; and

wherein the oxygen vacancy region is formed to have a depth of approximately two (2) nm to approximately five (5) nm from a top surface of the ferroelectric layer.

10. The method of claim 1 , wherein annealing the ferroelectric layer is performed after the gate electrode layer is formed on the ferroelectric layer and the gate electrode layer acts as a capping layer of the ferroelectric layer.

11. The method of claim 1 , wherein annealing the ferroelectric layer is performed at a temperature of approximately 500 degrees Celsius to approximately 1000 degrees Celsius.

12. The method of claim 1 , further comprising applying a second annealing process to the crystallized ferroelectric layer after the ferroelectric layer is crystallized,

wherein the second annealing process is performed using a hydrogen gas as an ambient gas.

13. The method of claim 1 , further comprising injecting fluorine ions into the crystallized ferroelectric layer after the ferroelectric layer is crystallized.

14. A method of fabricating a ferroelectric memory device, the method comprising:

preparing a substrate;

forming an interfacial insulation layer on the substrate;

forming a ferroelectric layer including a metal oxide material directly on the interfacial insulation layer;

applying a surface treatment process to the ferroelectric layer to increase a concentration of oxygen vacancies in the metal oxide material;

creating an electric field across the ferroelectric layer;

forming a gate electrode layer on the ferroelectric layer; and

annealing the ferroelectric layer to crystallize the ferroelectric layer using the gate electrode layer as a capping layer,

wherein the concentration of oxygen vacancies is located in a portion of the ferroelectric layer from a top surface of the ferroelectric layer into the bulk of the ferroelectric layer,

wherein the thickness of the portion of the ferroelectric layer with the concentration of oxygen vacancies is one-half the thickness of the ferroelectric layer, and

wherein the concentration of oxygen vacancies act as positive charges.

15. The method of claim 14 , wherein the metal oxide material includes at least one of a hafnium oxide (HfO) material and a zirconium oxide (ZrO) material.

16. The method of claim 14 , wherein the surface treatment process includes a plasma process that is performed using an inert gas.

17. The method of claim 14 , wherein the surface treatment process includes injecting a dopant into an upper region of the ferroelectric layer.

18. The method of claim 17 ,

wherein the ferroelectric layer includes a binary metal oxide material, and the dopant includes metal ions having a valence which is different from a valence of metal atoms in the binary metal oxide material.

19. The method of claim 14 ,

wherein a surface treated region is formed in the ferroelectric layer by the surface treatment process with a predetermined depth from a top surface of the ferroelectric layer; and

wherein a maximum value of the predetermined depth is about half the thickness of the ferroelectric layer.

20. The method of claim 14 , wherein annealing is performed at a temperature of approximately 500 degrees Celsius to approximately 1000 degrees Celsius.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2024
From: SK HYNIX INC.
To: MIMIRIP LLC
Reel/Frame 067335/0246 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 24, 2018
From: YOO, HYANGKEUN
To: SK HYNIX INC.
Reel/Frame 046185/0802 →
Priority Claims (1)
KR 10-2017-0089924 · Jul 14, 2017 · national
Continuity (1)
Related Publication 20190019683A1 · Jan 17, 2019
Cited By (1)
US 12,382,670