IP Library Granted Patent US 10,558,563
Granted Patent B2
US 10,558,563 · App. 16/017,195 · Granted Feb 11, 2020

Computing system and method for controlling storage device

Inventor: Shinichi Kanno (Tokyo, JP)
Assignee: Toshiba Memory Corporation
G06F12/0246G06F3/061G06F3/064G06F3/0659G06F3/0679G06F12/0253G06F12/0292G06F12/0891G06F2212/7201
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Quick Facts
Patent No.
US 10,558,563
App. No.
16/017,195
Granted
Feb 11, 2020
Kind
B2
Abstract

According to one embodiment, a computing system transmits to a storage device a write request designating a first logical address for identifying first data to be written and a length of the first data. The computing system receives from the storage device the first logical address and a first physical address indicative of both of a first block selected from blocks except a defective block by the storage device, and a first physical storage location in the first block to which the first data is written. The computing system updates a first table which manages mapping between logical addresses and physical addresses of the storage device and maps the first physical address to the first logical address.

Claims (60)

1. A computing system controlling a storage device comprising a plurality of nonvolatile memory dies each including a plurality of blocks,

the computing system comprising:

a memory; and

a processor electrically connected to the memory and configured to execute a computer program stored in the memory, wherein

the processor is configured:

to transmit to the storage device a write request designating a first logical address for identifying first data to be written and a length of the first data;

to receive from the storage device the first logical address and a first physical address indicative of both of a first block selected from blocks except a defective block as a write destination block for the first data, by the storage device, and a first physical storage location in the first block to which the first data is written; and

to update a first table which manages mapping between each of logical addresses and each of physical addresses of the storage device and to map the first physical address to the first logical address.

2. The computing system of claim 1 , wherein

the processor is configured:

to obtain the first physical address mapped to the first logical address by referring to the first table; and

to transmit a read request designating the first physical address to the storage device.

3. The computing system of claim 1 , wherein the processor is configured:

after the first data is copied from a previous physical storage location to a new physical storage location by the storage device, to receive from the storage device the first logical address, a second physical address indicative of the previous physical storage location, and a third physical address indicative of the new physical storage location;

to obtain a current physical address mapped to the first logical address by referring to the first table;

to update the first table and to map the third physical address to the first logical address when the second physical address matches the obtained current physical address; and

to maintain the current physical address without updating the first table when the second physical address does not match the obtained current physical address.

4. The computing system of claim 3 , wherein

the processor is configured to instruct the storage device to invalidate data corresponding to the second physical address by transmitting a first command designating the second physical address to the storage device, after updating the first table and mapping the third physical address to she first logical address.

5. The computing system of claim 1 , wherein

the processor is configured, when the first data is updated data of previous data already written to the storage device, to instruct the storage device to invalidate the previous data by transmitting a first command designating a physical address corresponding to the previous data to the storage device, after updating the first table and mapping the first physical address to the first logical address.

6. The computing system of claim 1 , wherein

the processor is configured, when the first data is updated data of previous data already written to the storage device and the previous data is duplicated data referred to by a plurality of logical addresses, to instruct the storage device to decrement a reference count indicative of a number of logical addresses referring to the previous data by transmitting a first command designating a physical address corresponding to the previous data to the storage device, after updating the first table and mapping the first physical address to the first logical address.

7. The computing system of claim 6 , wherein

the computing system does not maintain the reference count.

8. A computing system controlling a storage device, the storage device comprising a plurality of nonvolatile memory dies and configured to manage a plurality of parallel units each including blocks belonging to different nonvolatile memory dies, the system comprising:

a memory; and

a processor electrically connected to the memory and configured to execute a computer program stored in the memory, wherein

the processor is configured:

to transmit to the storage device a write request designating a first logical address for identifying first data to be written and a length of the first data;

to receive from the storage device the first logical address and a first physical address indicative of both of a first block selected from blocks except a defective block included in one parallel unit to be written, as a write destination block for the first data, by the storage device, and a first physical storage location in the first block to which the first data is written; and

to update a first table which manages mapping between each of logical addresses and each of physical addresses of the storage device and to map the first physical address to the first logical address.

9. The computing system of claim 8 , wherein

the write request designates the first logical address and a first block address indicative of one of the plural units, and

the one parallel unit to be written is a parallel unit having the designated first block address.

10. The computing system of claim 8 , wherein

the processor is configured:

to obtain the first physical address mapped to the first logical address by referring to the first table; and

to transmit a read request designating the first physical address to the storage device.

11. The computing system of claim 8 , wherein

the processor is configured:

after the first data is copied from a previous physical storage location to a new physical storage location by the storage device, to receive from the storage device the first logical address, a second physical address indicative of the previous physical storage location, and a third physical address indicative of the new physical storage location;

to obtain a current physical address mapped to the first logical address by referring to the first table;

to update the first table and to map the third physical address to the first logical address when the second physical address matches the obtained current physical address; and

to maintain the current physical address without updating the first. table when the second physical address does not match the obtained current physical address.

12. The computing system of claim 11 , wherein the processor is configured to instruct the storage device to invalidate data corresponding to the second physical address by transmitting a first command designating the second physical address to the storage device, after updating the first table and mapping the third physical address to the first logical address.

13. A method executed by a computing system controlling a storage device comprising a plurality of nonvolatile memory dies each including a plurality of blocks, the method comprising:

transmitting to the storage device a write request designating a first logical address for identifying first data to be written and a length of the first data;

receiving from the storage device the first logical address and a first physical address indicative of both of a first block selected from blocks except a defective block as a write destination block for the first data, by the storage device, and a first physical storage location in the first block to which the first data is written; and

updating a first table which manages mapping between each of logical addresses and each of physical addresses of the storage device and mapping the first physical address to the first logical address.

14. The method of claim 13 , further comprising:

obtaining the first physical address mapped to the first logical address by referring to the first table; and

transmitting a read request designating the first physical address to the storage device.

15. The method of claim 13 , further comprising:

after the first data is copied from a previous physical storage location to a new physical storage location by the storage device, receiving from the storage device the first logical address, a second physical address indicative of the previous physical storage location, and a third physical address indicative of the new physical storage location;

obtaining a current physical address mapped to the first logical address by referring to the first table;

updating the first table and mapping the third physical address to the first logical address when the second physical address matches the obtained current physical address; and

maintaining the current physical address without updating the first table when the second physical address does not match the obtained current physical address.

16. The method of claim 15 , further comprising:

instructing the storage device to invalidate data corresponding to the second physical address by transmitting a first command designating the second physical address to the storage device, after updating the first table and mapping the third physical address to the first logical address.

Assignments (4)
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2018
From: KANNO, SHINICHI
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 046192/0975 →
Priority Claims (1)
JP 2017-209344 · Oct 30, 2017 · national
Continuity (1)
Related Publication 20190129841A1 · May 2, 2019
Cited By (5)
US 12,271,266 US 12,298,853 US 12,306,717 US 12,321,236 US 12,399,782