Self-aligned silicide/germanide formation to reduce external resistance in a vertical field-effect transistor

1. A method for manufacturing a vertical transistor device, comprising:

forming a first plurality of fins in a first device region on a substrate;

forming a second plurality of fins in a second device region on the substrate;

forming a plurality of bottom source/drain regions on the substrate adjacent lower portions of each of the first and second plurality of fins in the first and second device regions;

forming a sacrificial layer in the first device region on a first bottom source/drain region of the plurality of bottom source/drain regions;

forming a bottom spacer layer on the plurality of bottom source/drain regions and the sacrificial layer;

forming a plurality of gate structures on the bottom spacer layer;

removing portions of the plurality of gate structures and of the bottom spacer layer to expose the sacrificial layer in the first device region and a second bottom source/drain region of the plurality of bottom source/drain regions in the second device region;

depositing a germanium oxide layer on the plurality of gate structures and on the exposed sacrificial layer and second bottom source/drain region; and

performing an annealing process to convert portions of the germanium oxide layer on the exposed sacrificial layer and second bottom source/drain region to at least one of a plurality of silicide layers and a plurality of germanide layers.

2. The method according to claim 1 , wherein the germanium oxide layer is a metal-doped germanium oxide layer.

3. The method according to claim 1 , wherein the germanium oxide layer is conformally deposited.

4. The method according to claim 1 , wherein the sacrificial layer is epitaxially grown.

5. The method according to claim 4 , wherein the sacrificial layer comprises silicon germanium.

6. The method according to claim 1 , wherein the annealing process is performed at a temperature in the range of about 500° C. to about 700° C.

7. The method according to claim 1 , wherein the at least one of the plurality of silicide layers and the plurality of germanide layers are formed around the first and second plurality of fins on multiple sides of each of the first and second plurality of fins.

8. The method according to claim 1 , further comprising forming a plurality of contacts to the plurality of bottom source/drain regions, wherein the at least one of the plurality of silicide layers and the plurality of germanide layers are formed around all sides of the plurality of contacts.

9. The method according to claim 1 , wherein the first and second device regions respectively comprise n-type and p-type transistor regions.

10. The method according to claim 1 , further comprising covering a gate contact region with a mask during the removal of the portions of the plurality of gate structures and of the bottom spacer layer.

11. The method according to claim 1 , further comprising depositing a top spacer layer on the plurality of gate structures, wherein the top spacer layer is formed between the plurality of gate structures and at least a portion of the germanium oxide layer.

12. The method according to claim 1 , further comprising depositing a liner layer on unconverted portions of the germanium oxide layer and on the at least one of the plurality of silicide layers and the plurality of germanide layers.

13. The method according to claim 1 , further comprising:

conformally depositing a top spacer layer on the plurality of gate structures; and

conformally depositing a dielectric layer on the top spacer layer prior to the removal of the portions of the plurality of gate structures and of the bottom spacer layer.

14. The method according to claim 1 , wherein:

the removal of the portions of the plurality of gate structures and of the bottom spacer layer forms openings over the exposed sacrificial layer and second bottom source/drain region between remaining portions of the plurality of gate structures and the bottom spacer layer; and

the germanium oxide layer fills in the openings.

15. A method for manufacturing a vertical transistor device, comprising:

forming a first plurality of fins in a first device region on a substrate;

forming a second plurality of fins in a second device region on the substrate;

epitaxially growing a plurality of bottom source/drain regions on the substrate adjacent lower portions of each of the first and second plurality of fins in the first and second device regions;

epitaxially growing a sacrificial layer in the first device region on a first bottom source/drain region of the plurality of bottom source/drain regions;

forming a plurality of gate structures on the plurality of bottom source/drain regions and the sacrificial layer;

removing portions of the plurality of gate structures to expose the sacrificial layer in the first device region and a second bottom source/drain region of the plurality of bottom source/drain regions in the second device region;

depositing a metal-doped germanium oxide layer on the plurality of gate structures and on the exposed sacrificial layer and second bottom source/drain region; and

performing an annealing process to convert portions of the metal-doped germanium oxide layer on the exposed sacrificial layer and second bottom source/drain region to at least one of a plurality of silicide layers and a plurality of germanide layers.