IP Library › Granted Patent US 10,741,748
Granted Patent B2
US 10,741,748 · App. 16/017,417 · Granted Aug 11, 2020

Back end of line metallization structures

Inventors: Joseph F. Maniscalco (Lake Katrine, NY); Raghuveer R. Patlolla (Guilderland, NY); Cornelius Brown Peethala (Slingerlands, NY); Chih-Chao Yang (Glenmont, NY)
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
H01L43/02H01F10/3254H01L21/7684H01L21/76802H01L21/76831H01L21/76843H01L21/76877H01L23/528H01L23/5226H01L27/222H01L43/12H01L23/53238
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,741,748
App. No.
16/017,417
Granted
Aug 11, 2020
Kind
B2
Abstract

Back end of line (BEOL) metallization structures and methods according to aspects of the invention generally include forming an interconnect structure including a recessed via structure in an interlayer dielectric. The recessed via structure is lined with a liner layer and filled with a first metal such as copper, tungsten, aluminum, alloys thereof or mixtures thereof. The recessed portion is filled with a second metal such as tantalum, titanium, tungsten, cobalt, ruthenium, iridium, platinum, nitrides thereof, or mixtures thereof, which in combination with the liner layer provides effective barrier properties for the bulk first metal.

Claims (9)

1. A back end of line (BEOL) metallization structure comprising:

a first interconnect structure comprising an interlayer dielectric and one or more metal filled trenches therein;

a second interconnect structure overlying the first interconnect structure, the second interconnect structure comprising an interlayer dielectric including at least one via including a liner layer on a bottom surface of the at least one via and on sidewalls extending from the bottom surface, a first metal in the at least one via having a recessed top surface below a plane defined by a top surface of the interlayer dielectric; and

a third interconnect structure overlying the second interconnect structure, the third interconnect structure comprising an interlayer dielectric including a trench, wherein the at least one via of the second interconnect structure is configured to provide a conductive pathway between the first and third interconnect structures, wherein a second metal fills the recessed top surface of the at least one via the filling and extends above a plane defined by a top surface of the interlayer dielectric of the second interconnect structure such that the liner laser in the at least one via of the second interconnect and the second metal encapsulate the metal filled recessed via structure, and wherein the first metal is different from the second metal and comprises copper, tungsten, aluminum, alloys thereof or combinations thereof, and wherein the second metal comprises tantalum, tungsten, titanium cobalt, ruthenium, iridium, platinum, alloys thereof, or combinations thereof.

2. The back end of line (BEOL) metallization structure of claim 1 , wherein the trench in the third interconnect provides an interconnect line.

3. The back end of line (BEOL) metallization structure of claim 1 , wherein the trench in the third interconnect provides a bottom electrode of a multilayer structure within the trench.

4. The back end of line (BEOL) metallization structure of claim 3 , wherein the multilayer structure is a magnetoresistive random access memory (MRAM) device.

5. The back end of line (BEOL) metallization structure of claim 1 , wherein the second metal in the second interconnect structure extends into the trench of the third interconnect structure to define a bottom electrode, wherein the bottom electrode has a top planar surface.

6. The back end of line (BEOL) metallization structure of claim 1 , wherein the interlayer dielectric in the first, second, and third interconnect structures comprises a low k dielectric material, an oxide, SiN, SiC, SiC (N,H).

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 9, 2018
From: MANISCALCO, JOSEPH F.; PATLOLLA, RAGHUVEER R.; PEETHALA, CORNELIUS BROWN; YANG, CHIH-CHAO
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 046290/0096 →
Continuity (1)
Related Publication 20190393409A1 · Dec 26, 2019