Vertical field effect transistor with reduced parasitic capacitance
Embodiments are directed to a method and resulting structures for a semiconductor device having reduced parasitic capacitance. A semiconductor fin is formed on a substrate. A first bottom spacer is formed on a surface of the substrate and a sidewall of the semiconductor fin. A sacrificial spacer is formed over a channel region of the semiconductor fin and a portion of the first bottom spacer. A second bottom spacer is formed on a surface of the first bottom spacer and adjacent to the sacrificial spacer. The sacrificial spacer is removed and a conductive gate is formed over the channel region of the semiconductor fin.
1. A method for forming a semiconductor device, the method comprising:
forming a semiconductor fin on a substrate;
forming a first bottom spacer on a surface of the substrate such that a portion of the first bottom spacer is in direct contact with a sidewall of the semiconductor fin, the first bottom spacer comprising a first portion and a second portion;
forming a sacrificial spacer over the sidewall of the semiconductor fin and directly on the first portion of the first bottom spacer;
forming a second bottom spacer directly on the second portion of the first bottom spacer and adjacent to a sidewall of the sacrificial spacer, the sacrificial spacer preventing the second bottom spacer from forming directly on the first portion of the first bottom spacer;
removing the sacrificial spacer to expose the first portion of the first bottom spacer; and
forming a conductive gate over a channel region of the semiconductor fin;
wherein the first bottom spacer and the second bottom spacer define a continuous bottom spacer region having a first thickness in a near channel region and a second, greater thickness in a non-channel region, the near channel region between the non-channel region and the sidewall of the semiconductor fin.
2. The method of claim 1 further comprising forming a second semiconductor fin on the substrate.
3. The method of claim 2 , wherein forming the second bottom spacer on a surface of the first bottom spacer comprises forming a portion of the second bottom spacer between the semiconductor fins.
4. The method of claim 1 , wherein the first bottom spacer and the second bottom spacer each comprise a dielectric material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.
5. The method of claim 1 further comprising recessing the second portion of the conductive gate.
6. The method of claim 5 further comprising forming a top spacer over the partially recessed conductive gate.