Early detection of execution errors
Certain aspects of the present disclosure provide apparatus and techniques for communicating error information during memory operations. For example, certain aspects of the present disclosure may provide a method for memory operations. The method generally including receiving a command from a host device, performing memory operations corresponding to the command received from the host device, detecting an error during the memory operations, and communicating the error based on the detection, wherein the error is communicated before receiving another command from the host device.
1. A method for performing memory operations, comprising:
receiving, by a device controller, a command from a host device, wherein a plurality of data lines are coupled between the device controller and the host device for indicating data to be written to memory;
performing, by the device controller, memory operations corresponding to the command received from the host device;
detecting, by the device controller, an error during the memory operations; and
communicating, by the device controller, the error based on the detection, wherein the error is communicated via a data line of the plurality of data lines before receiving another command from the host device.
2. The method of claim 1 , wherein:
the command comprises an erase command; and
the memory operations comprise erasing one or more memory location of the memory in response to the erase command.
3. The method of claim 1 , wherein:
the command comprises a write command;
the method further comprises receiving, via the plurality of data lines, the data to be written to the memory corresponding to the write command; and
the memory operations comprise writing the data to the memory.
4. The method of claim 3 , wherein receiving the data comprises receiving a plurality of data blocks to be written to the memory, wherein the error is communicated after a last data block of the plurality of data blocks is received.
5. The method of claim 4 , wherein the error is communicated during a busy cycle, the busy cycle being after the last data block of the plurality of data blocks is received.
6. The method of claim 5 , further comprising setting the data line of the plurality of data lines to logic low during the busy cycle until the error is detected.
7. The method of claim 1 , wherein:
communicating the error comprises setting the data line of the plurality of data lines for multiple consecutive clock cycles in accordance with a bit pattern.
8. The method of claim 7 , wherein setting the data line in accordance with the bit pattern comprises setting the data line to logic high during a first clock cycle, to logic low during a second clock cycle, and to logic high during a third clock cycle, the second clock cycle being between the first clock cycle and the third clock cycle.
9. The method of claim 7 , wherein the data line comprises a least significant bit data line of the plurality of data lines.
10. The method of claim 1 , wherein the memory operations comprises writing data to or erasing data from an embedded multimedia card (eMMC) flash memory.
11. The method of claim 1 , wherein the error comprises a write protect error.
12. A method for performing memory operations, comprising:
sending, by a host device, a command to a device controller for performing memory operations, a plurality of data lines being coupled between the device controller and the host device for indicating data to be written to memory;
sampling, by the host device, a data line of the plurality of data lines before sending another command; and
detecting, by the host device, whether an error has occurred during the memory operations based on the sampling of the data line.
13. The method of claim 12 , wherein the command for performing memory operations comprises an erase command for erasing one or more memory location of the memory.
14. The method of claim 12 , wherein:
the command comprises a write command;
the method further comprises sending the data, via the plurality of data lines, to be written to the memory corresponding to the write command; and
the data line is sampled after sending the data.
15. The method of claim 14 , wherein sending the data comprises sending a plurality of data blocks to be written to the memory, wherein the data line is sampled to detect the error after a last data block of the plurality of data blocks is sent.
16. The method of claim 15 , wherein the error is detected during a busy cycle, the busy cycle being after the last data block of the plurality of data blocks is sent.
17. The method of claim 16 , wherein the data line of the plurality of data lines is set to logic low during the busy cycle until the error is detected.
18. The method of claim 12 , wherein:
detecting whether the error occurred comprises detecting a bit pattern on the data line across multiple consecutive clock cycles.
19. The method of claim 18 , wherein detecting the bit pattern comprises detecting the data line at logic high during a first clock cycle, at logic low during a second clock cycle, and at logic high during a third clock cycle, the second clock cycle being between the first clock cycle and the third clock cycle.
20. An apparatus for performing memory operations, comprising:
a memory; and
a device controller coupled to the memory and configured to:
receive, by the device controller, a command from a host device, a plurality of data lines being coupled between the device controller and the host device for indicating data to be written to the memory;
perform, by the device controller, memory operations corresponding to the command received from the host device;
detect, by the device controller, an error during the memory operations; and
communicate, by the device controller, the error based on the detection, wherein the error is communicated via a data line of the plurality of data lines before receiving another command from the host device.