Ferroelectric memory array with variable plate-line architecture
A ferroelectric memory array includes (a) a driver circuit providing a first signal and a second signal; (b) word lines each providing a word line signal; and (c) memory array sections. Each memory array section may include: (a) bit lines; (b) plate line segments each associated with a corresponding one of the word line signals; (c) local plate line decoders, each local plate line decoder (i) being associated with one of the plate line segments, (ii) receiving the corresponding word line signal of the associated plate line segment, the first signal and the second signal, and (iii) providing predetermined voltages on the associated plate line segment according to the received word line signal, the first signal and the second signal; and (d) memory cells, each memory cells having one or more ferroelectric capacitor connected between one of the plate line segments and one of the bit lines. The predetermined voltages output from a local plate decoder may include a voltage of the word line signal, a power supply voltage, or one half the power supply voltage.
1. A ferroelectric memory array comprising:
a driver circuit providing as output a first signal and a second signal;
a plurality of word lines each providing a word line signal; and
a plurality of memory array sections, each memory array section comprising:
a plurality of bit lines;
a plurality of plate line segments each associated with a corresponding one of the word line signals;
a plurality of local plate line decoders, each local plate line decoder (i) being associated with one of the plate line segments, (ii) receiving as input the corresponding word line signal of the associated plate line segment, the first signal and the second signal, and (iii) providing as output one of a plurality of predetermined voltages on the associated plate line segment according to the received word line signal, the first signal and the second signal; and
a plurality of memory cells, each memory cells having one or more ferroelectric capacitor connected between one of the plate line segments and one of the bit lines.
2. The ferroelectric memory array of claim 1 , wherein the predetermined voltages include a voltage of the word line signal.
3. The ferroelectric memory array of claim 1 , wherein the ferroelectric memory array receives a power supply voltage, and wherein the predetermined voltages include the power supply voltage and one half the power supply voltage.
4. The ferroelectric memory array of claim 3 , wherein a write operation on a memory cell includes imposing a voltage difference across at least one of the ferroelectric capacitors of the memory cell that equals substantially the power supply voltage.
5. The ferroelectric memory array of claim 3 , wherein a write operation on a memory cell includes imposing a voltage difference across at least one of the ferroelectric capacitors of the memory cell that equals substantially one half the power supply voltage.
6. The ferroelectric memory array of claim 1 , wherein the memory array further comprises a signal generation circuit that operates selectively under a first mode and a second mode, wherein the signal generation circuit generates different signal values for the first signal and the second signal according to whether it is operating in the first mode or in the second mode.
7. The ferroelectric memory array of claim 6 wherein, under the first mode, the first and second signals each switch between two predetermined power supply voltages and wherein, under the second mode, the first and second signals each have a constant voltage.
8. The ferroelectric memory array of claim 7 , wherein the constant voltage equals substantially to one half of one of the two predetermined power supply voltages.
9. The ferroelectric memory array of claim 6 , wherein a data retention time associated with a write operation under the first mode is substantially longer than a data retention time associated with a write operation under the second mode.
10. The ferroelectric memory array of claim 1 , each memory array section further comprises a plurality of sense amplifiers sensing a voltage one or more associated bit lines.
11. The ferroelectric memory array of claim 1 , wherein the memory array sections are each organized under an open bit line architecture.
12. The ferroelectric memory array of claim 1 , wherein each memory cell comprises two ferroelectric capacitors configured to hold true and complement representations of a data value.