IP Library Granted Patent US 10,930,743
Granted Patent B2
US 10,930,743 · App. 16/020,240 · Granted Feb 23, 2021

Layered structure, semiconductor device including layered structure, and semiconductor system including semiconductor device

Inventors: Tokiyoshi Matsuda (Kyoto, JP); Takashi Shinohe (Kyoto, JP); Toshimi Hitora (Kyoto, JP)
Assignee: FLOSFIA INC.
H01L29/24C23C16/40C23C16/4486H01L21/0242H01L21/0259H01L21/0262H01L21/02483H01L21/02488H01L21/02494H01L21/02565H01L21/02576H01L21/02579H01L21/02581H01L21/02628H01L27/1229H01L29/04H01L29/0891H01L29/66969H01L29/737H01L29/7371H01L29/7786H01L29/7787H01L29/786H01L29/7869C23C16/44
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Quick Facts
Patent No.
US 10,930,743
App. No.
16/020,240
Granted
Feb 23, 2021
Kind
B2
Abstract

In a first aspect of a present inventive subject matter, a layered structure includes a first semiconductor layer including an ε-phase crystalline oxide semiconductor with a first composition, and a second semiconductor layer including an ε-phase crystalline oxide semiconductor with a second composition that is different from the first composition of the first semiconductor layer, and the second semiconductor layer is layered on the first semiconductor layer.

Claims (49)

1. A layered structure, comprising:

a first semiconductor layer comprising a first ε-phase crystalline oxide semiconductor with a first composition; and

a second semiconductor layer comprising a second ε-phase crystalline oxide semiconductor with a second composition that is different from the first composition of the first semiconductor layer, the second semiconductor layer layered on the first semiconductor layer.

2. The layered structure of claim 1 , wherein

the first semiconductor layer comprises as a major metal component at least one selected from among gallium, indium and aluminum.

3. The layered structure of claim 1 , wherein

the first semiconductor layer comprises a mixed crystal, the mixed crystal comprising as a major metal component at least two selected from among gallium, indium and aluminum.

4. The layered structure of claim 1 , wherein

the first semiconductor layer comprises ε-Ga 2 O 3 .

5. The layered structure of claim 1 , wherein

the first semiconductor layer comprises a mixed crystal comprising ε-Ga 2 O 3 .

6. The layered structure of claim 1 , wherein

the second semiconductor layer comprises gallium as a major metal component.

7. The layered structure of claim 1 , wherein

the second semiconductor layer comprises ε-Ga 2 O 3 .

8. The layered structure of claim 1 , wherein

the second semiconductor layer comprises a mixed crystal comprising ε-Ga 2 O 3 .

9. The layered structure of claim 1 , wherein

the second semiconductor layer comprises aluminum.

10. The layered structure of claim 1 , wherein

the second semiconductor layer comprises (GaInAl) 2 O 3 .

11. The layered structure of claim 1 , further comprising:

three or more semiconductor layers comprising the first semiconductor layer and the second semiconductor layer.

12. The layered structure of claim 1 , further comprising:

a heterojunction between the first semiconductor layer and the second semiconductor layer.

13. The layered structure of claim 11 , further comprising:

a heterojunction between two semiconductor layers selected from among the three or more semiconductor layers.

14. The layered structure of claim 11 , further comprising:

an electrically insulating layer.

15. A semiconductor device, comprising:

a layered structure comprising:

a first semiconductor layer comprising a first ε-phase crystalline oxide semiconductor with a first composition; and

a second semiconductor layer comprising a second ε-phase crystalline oxide semiconductor with a second composition that is different from the first composition of the first semiconductor layer, the second semiconductor layer layered on the first semiconductor layer;

a first electrode electrically connected to the layered structure; and

a second electrode electrically connected to the layered structure.

16. The semiconductor device of claim 15 , wherein

the semiconductor device is a power device.

17. The semiconductor device of claim 16 , wherein

the semiconductor device is a semiconductor device with a high-frequency characteristic.

18. The semiconductor device of claim 16 , wherein

the semiconductor device is a high-electron-mobility transistor or a heterojunction bipolar transistor.

19. A system, comprising:

a circuit board; and

a semiconductor device comprising:

a layered structure comprising:

a first semiconductor layer comprising a first ε-phase crystalline oxide semiconductor with a first composition; and

a second semiconductor layer comprising a second ε-phase crystalline oxide semiconductor with a second composition that is different from the first composition of the first semiconductor layer, the second semiconductor layer layered on the first semiconductor layer;

a first electrode electrically connected to the layered structure; and

a second electrode electrically connected to the layered structure.

Assignments (2)
CHANGE OF ASSIGNEE ADDRESS Recorded Jun 6, 2019
From: FLOSFIA INC.
To: FLOSFIA INC.
Reel/Frame 049393/0558 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 27, 2018
From: MATSUDA, TOKIYOSHI; SHINOHE, TAKASHI; HITORA, TOSHIMI
To: FLOSFIA INC.
Reel/Frame 046217/0163 →
Priority Claims (2)
JP JP2017-126568 · Jun 28, 2017 · national
JP JP2017-191609 · Sep 29, 2017 · national
Continuity (1)
Related Publication 20190006472A1 · Jan 3, 2019