Read network topology
A read network topology for a matrix output device with a number of outputs determined by cross-joining “m” rows and “n” columns comprises a basic filtering block replicated for all the outputs and separately assigned to each of the outputs; each filtering block contains two filtering circuits that have a common input connection to the assigned matrix output and that provide two separate symmetrical and filtered outputs; all the row outputs (i) from the same row “i” but from different columns are interconnected to an input of an amplifier linked to row “i”, and all the column outputs (j) from the same column “j” but from different rows are connected together to an input of an amplifier linked to column “j”, the complete topology appearing when “i” and “j” are expanded in the respective intervals thereof.
1. A readout network topology for a Matrix Output Device with a plurality of matrix outputs given by the cross combination of “m” rows and “n” columns, labeled as Source(i, j), wherein “i” ranges 1 to m and “j” ranges 1 to n, the readout network topology comprising a basic frequency filtering block, replicated for each of the matrix outputs, and separately assigned to each matrix output; wherein:
each frequency filtering block includes a pair of filtering circuits having a common input connection to its assigned matrix output and providing two separate, symmetrical and filtered outputs labeled Col. (j) and Row(i);
all the Row(i) outputs incoming from the same row “i”, but different columns are connected together to the low impedance input of an amplifier linked to the “i” row, that completes the active filtering and the mixing topology of the whole path, giving rise to the corresponding AmpRow(i) output; and
all the Column(j) outputs incoming from the same column “j”, but different rows, are connected together to the low impedance input of an amplifier linked to the “j” column, that completes the frequency active filtering and the mixing topology of the whole path, giving rise to the corresponding AmpCol(j) output, wherein the frequency filtering block is made of either a pair of CR Filtering Circuits or a pair of CL Filtering Circuits.
2. The readout network topology according to claim 1 , wherein the different common outputs of the Filtering blocks, for rows, Row(i), and for columns, Column(j), are connected to amplifier circuits of the types “of charge” or “of current”, with low input impedance, compared with the impedance of the Filtering circuit, being at least 10 times lower.
3. The readout network topology according to claim 1 , wherein the different common outputs of the filtering blocks, for rows, Row(i), and for columns, Column(j), are connected to the negative inputs of the amplifier circuits and a resistor is used in a feedback loop between an output of an OpAmp in the amplifier circuit and its negative input.
4. The readout network topology according to claim 1 , wherein a totality of the different common outputs of the Filtering blocks, for rows, Row(i), and for columns, Column(j), represents a totality of outputs of the detector to be digitized.
5. The readout network topology according to claim 1 wherein different Amplifier outputs for rows, AmpRow(i) and for columns, AmpCol(j), represent outputs of a detector to be digitized.
6. The readout network topology according to claim 5 wherein a first resistor chain interconnects the outputs of all rows AmpRow(i) and a second resistor chain interconnects the outputs of all columns, AmpCol(j); the ends of the resistor chains enable to extract directly, in real time, the “x” and “y” position by means of a Center of Gravity algorithm.
7. The readout network topology according to claim 6 wherein an adding circuit is provided to add the signals obtained at the different interconnection points of the resistor chain for rows, AmpRow(i), and for columns, AmpCol(j), the values of which are used to obtained a Depth of Interaction (DOI), inside a continuous crystal coupled to the matrix output device.
8. The readout network topology of claim 1 wherein the matrix output device is selected from a SiPMA matrix.
9. The readout network topology of claim 1 , wherein the matrix output device is coupled to continuous monolithic scintillator crystals, or pixelated scintillators.
10. A matrix output device comprising the readout network topology with a plurality of matrix outputs given by the cross combination of “m” rows and “n” columns, labeled as Source(i, j), wherein “i” ranges 1 to m and “j” ranges 1 to n, the readout network topology comprising a basic frequency filtering block, replicated for each of the matrix outputs, and separately assigned to each matrix output; wherein:
each frequency filtering block includes a pair of filtering circuits having a common input connection to its assigned matrix output and providing two separate, symmetrical and filtered outputs labeled Col. (j) and Row(i);
all the Row(i) outputs incoming from the same row “i”, but different columns are connected together to the low impedance input of an amplifier linked to the “i” row, that completes the active filtering and the mixing topology of the whole path, giving rise to the corresponding AmpRow(i) output; and
all the Column(j) outputs incoming from the same column “j”, but different rows, are connected together to the low impedance input of an amplifier linked to the “j” column, that completes the frequency active filtering and the mixing topology of the whole path, giving rise to the corresponding AmpCol(j) output, wherein the frequency filtering block is made of either a pair of CR Filtering Circuits or a pair of CL Filtering Circuits.
11. The matrix output device according to claim 10 is a SiPMA matrix.
12. The matrix output device according to claim 11 that is a SiPMA that is coupled to a monolithic crystal.
13. The matrix output device according to claim 10 that is coupled to continuous monolithic scintillation crystals.
14. A detector block characterized in that it comprises a matrix output device, which comprises a readout network topology with a plurality of matrix outputs given by the cross combination of “m” rows and “n” columns, labeled as Source(i, j), wherein “i” ranges 1 to m and “j” ranges 1 to n, the readout network topology comprising a basic frequency filtering block, replicated for each of the matrix outputs, and separately assigned to each matrix output; wherein:
each frequency filtering block includes a pair of filtering circuits having a common input connection to its assigned matrix output and providing two separate, symmetrical and filtered outputs labeled Col. (j) and Row(i);
all the Row(i) outputs incoming from the same row “i”, but different columns are connected together to the low impedance input of an amplifier linked to the “i” row, that completes the active filtering and the mixing topology of the whole path, giving rise to the corresponding AmpRow(i) output; and
all the Column(j) outputs incoming from the same column “j”, but different rows, are connected together to the low impedance input of an amplifier linked to the “j” column, that completes the frequency active filtering and the mixing topology of the whole path, giving rise to the corresponding AmpCol(j) output, wherein the frequency filtering block is made of either a pair of CR Filtering Circuits or a pair of CL Filtering Circuits.
15. The detector block according to claim 14 , wherein the matrix output device is a SiPMA.
16. The detector block according to claim 14 , wherein the matrix output device is coupled to a continuous monolithic scintillation crystal or a pixelated scintillation crystal.
17. The detector block according to claim 16 , wherein the matrix output device is a SiPMA and is coupled to a continuous monolithic crystal.
18. A process for obtaining images generated by X-ray sources or gamma ray sources comprising detecting the X-ray or gamma ray, and processing the signal obtained by means of a readout network topology with a plurality of matrix outputs given by the cross combination of “m” rows and “n” columns, labeled as Source(i, j), wherein “i” ranges 1 to m and “j” ranges 1 to n, the readout network topology comprising a basic frequency filtering block, replicated for each of the matrix outputs, and separately assigned to each matrix output; wherein:
each frequency filtering block includes a pair of filtering circuits having a common input connection to its assigned matrix output and providing two separate, symmetrical and filtered outputs labeled Col. (j) and Row(i);
all the Row(i) outputs incoming from the same row “i”, but different columns are connected together to the low impedance input of an amplifier linked to the “i” row, that completes the active filtering and the mixing topology of the whole path, giving rise to the corresponding AmpRow(i) output; and
all the Column(j) outputs incoming from the same column “j”, but different rows, are connected together to the low impedance input of an amplifier linked to the “j” column, that completes the frequency active filtering and the mixing topology of the whole path, giving rise to the corresponding AmpCol(j) output, wherein the frequency filtering block is made of either a pair of CR Filtering Circuits or a pair of CL Filtering Circuits.
19. The process of claim 18 , wherein the readout network topology is included in a matrix output device.
20. The process of claim 18 , wherein the matrix output device is comprised in a detector block.