Memory device performing UV-assisted erase operation
A nonvolatile memory device includes: a plurality of word lines that are stacked; a pillar structure that penetrates through the word lines in a vertical direction; and a voltage supplier suitable for supplying a plurality of biases that are required according to an operation mode, to the word lines and the pillar structure. The pillar structure includes: a vertical channel region disposed in a core; and a laser diode structure disposed between the word lines and the vertical channel region to surround a periphery of the vertical channel region.
1. A nonvolatile memory device, comprising:
a plurality of word lines that are stacked;
a pillar structure that penetrates through the word lines in a vertical direction; and
a voltage supplier suitable for supplying a plurality of biases that are required according to an operation mode, to the word lines and the pillar structure,
wherein the pillar structure includes:
a vertical channel region disposed in a core; and
a laser diode structure disposed between the word lines and the vertical channel region to surround a periphery of the vertical channel region.
2. The nonvolatile memory device of claim 1 , wherein the laser diode structure includes:
an n-type ITT-V-group compound layer and a p-type ITT-V-group compound layer that are disposed to sequentially surround the vertical channel region.
3. The nonvolatile memory device of claim 1 , wherein the laser diode structure includes:
an n-type GaN layer and a p-type GaN layer that are disposed to sequentially surround the vertical channel region.
4. The nonvolatile memory device of claim 3 , wherein the vertical channel region includes a silicon layer.
5. The nonvolatile memory device of claim 3 , wherein the p-type GaN layer has a lightly doped p-region and an intrinsic region.
6. The nonvolatile memory device of claim 3 , wherein during an erase operation, an erase bias is applied to the p-type GaN layer and a ground voltage is applied to the n-type GaN layer.
7. The nonvolatile memory device of claim 3 , further comprising:
a gate dielectric structure provided between the word lines and the laser diode structure.
8. The nonvolatile memory device of claim 7 , wherein the gate dielectric structure includes:
a tunneling dielectric layer, a charge trapping layer, and a blocking dielectric layer that sequentially surround the laser diode structure in the pillar structure.
9. The nonvolatile memory device of claim 7 , wherein the gate dielectric structure includes:
a tunneling dielectric layer and a charge trapping layer that sequentially surround the laser diode structure in the pillar structure; and
a blocking dielectric layer provided between the pillar structure and the word lines.
10. A nonvolatile memory device, comprising:
a plurality of word lines that are stacked;
a vertical channel region that penetrates through the word lines in a vertical direction; and
a GaN-based laser diode structure that is disposed to surround the vertical channel region and emits ultraviolet light during an erase operation.
11. The nonvolatile memory device of claim 10 , wherein the laser diode structure includes:
an n-type GaN layer and a p-type GaN layer that are disposed to sequentially surround the vertical channel region.
12. The nonvolatile memory device of claim 11 , wherein the vertical channel region includes a silicon layer.
13. The nonvolatile memory device of claim 11 , wherein the p-type GaN layer has a lightly doped p-region and an intrinsic region.
14. The nonvolatile memory device of claim 11 , wherein during the erase operation, an erase bias is applied to the p-type GaN layer and a ground voltage is applied to the n-type GaN layer.