Cache coherent, high-throughput input/output controller

1. An integrated circuit comprising:

an interface configured to couple to processing circuitry, wherein the interface comprises a cache memory and wherein the interface is configured to couple to the processing circuitry using a cache coherent data link that comprises a cache coherent protocol;

an input/output controller configured to couple to an input/output device;

functional circuitry configured to perform at least a first data operation; and

switch fabric configured to route data between the cache memory of the interface and the functional circuitry, the interface and the input/output controller, or the functional circuitry and the input/output controller.

2. The integrated circuit of claim 1 , wherein the first data operation comprises a compression operation, a decompression operation, an encryption operation, a decryption operation, an error checking operation, or a mathematical transformation, or any combination thereof.

3. The integrated circuit of claim 1 , wherein the integrated circuit comprises a programmable fabric that comprises the interface, the input/output controller, the functional circuitry, or the switch fabric, or any combination thereof.

4. The integrated circuit of claim 1 , wherein the interface comprises a Peripheral Component Interface Express (PCIe) interface.

5. The integrated circuit of claim 1 , wherein the input/output controller comprises a non-volatile memory extended (NVMe) controller, and wherein the input/output device comprises a non-volatile memory device.

6. The integrated circuit of claim 1 , wherein the switch fabric is coupled to the cache memory of the interface via a second cache coherent data link that comprises the cache coherent protocol.

7. The integrated circuit of claim 6 , comprising a second interface configured to couple to the processing circuitry.

8. An electronic device, comprising:

a processor;

a storage device; and

an integrated circuit comprising:

an interface coupled to the processor;

a storage controller coupled to the storage device;

functional circuitry configured to perform a first data operation; and

switch fabric configured to route data between the interface, the storage device, and the functional circuitry.

9. The electronic device of claim 8 , wherein the storage device comprises a hard disk (HD), a solid-state drive (SSD) disk, or a random access memory disk (RAMdisk), or any combination thereof.

10. The electronic device of claim 8 wherein the storage controller comprises a non-volatile memory express (NVMe) controller, a serial AT adaptor (SATA) controller, or both.

11. The electronic device of claim 8 , comprising a first data link coupling the integrated circuit to the processor and a second data link coupling the integrated circuit to the storage device, wherein a first bandwidth of the first data link is higher than a bandwidth of the second data link, wherein the functional circuitry is configured to perform a compression operation, and decompression operation.

12. The electronic device of claim 11 , wherein the processor is configured to write data to the storage device by:

sending the data to the interface;

routing, using the switch fabric, the data from the interface to the functional circuitry;

requesting performance of the compression operation over the data in the functional circuitry; and

routing, using the switch fabric, the data from the functional circuitry to the storage controller.

13. The electronic device of claim 11 , wherein the processor is configured to read data from the storage device by:

requesting data from the storage device via the storage controller;

routing, using the switch fabric, the data from the storage controller to the functional circuitry;

requesting performance of the decompression operation over the data in the functional circuitry; and

routing, using the switch fabric, the data from the functional circuitry to the interface.

14. The electronic device of claim 8 , wherein the functional circuitry is configured to perform an error detection or error correction operation.

15. The electronic device of claim 8 , comprising a cache coherent domain comprising the processor and a cache of the interface.

16. The electronic device of claim 15 , comprising an operating memory coupled to the processor, wherein the cache coherent domain comprises the operating memory.

17. The electronic device of claim 8 , comprising a system on chip (SoC) that comprises the processor and the integrated circuit.

18. The electronic device of claim 8 , wherein the integrated circuit comprises a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a hybrid device comprising hardened circuitry and programmable fabric.

19. A method comprising:

sending, from a processor, data to an interface of an integrated circuit using a first data link that comprises a first bandwidth;

requesting a switch fabric of the integrated circuit to route the data to functional circuitry of the integrated circuit;

requesting, from the functional circuitry, compression of the data;

receiving, from the integrated circuit, a notification of completion of the compression of the data by the functional circuitry; and

requesting the switch fabric of the integrated circuit to route the data from the functional circuitry to a storage device coupled to the integrated circuit using a second data link, wherein the second data link comprises a second bandwidth that is smaller than the first bandwidth.

20. The method of claim 19 , comprising requesting from the functional circuitry, an error checking operation of the data.