IP Library Granted Patent US 10,672,895
Granted Patent B2
US 10,672,895 · App. 16/023,418 · Granted Jun 2, 2020

Method for manufacturing a bipolar junction transistor

Inventors: Dirk Manger (Dresden, DE); Stefan Tegen (Dresden, DE)
Assignee: Infineon Technologies Dresden GmbH
H01L29/7378H01L29/0649H01L29/0653H01L29/0817H01L29/0826H01L29/1004H01L29/165H01L29/1608H01L29/36H01L29/66068H01L29/66242H01L29/7371
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Quick Facts
Patent No.
US 10,672,895
App. No.
16/023,418
Granted
Jun 2, 2020
Kind
B2
Abstract

Embodiments provide a method for manufacturing a bipolar junction transistor, comprising: providing a semiconductor substrate comprising a buried layer of a first conductive type; doping the semiconductor substrate in a collector implant region, to obtain a collector implant of the first conductive type extending parallel to a surface of the semiconductor substrate and from the surface of the semiconductor substrate to the buried layer; providing a base layer of a second conductive type on the surface of the semiconductor substrate, the base layer covering the collector implant; providing a sacrificial emitter structure on the base layer, wherein a projection of an area of the sacrificial emitter structure is enclosed by an area of the collector implant; and partially counter doping the collector implant through an area of the base layer surrounding an area of the base layer that is covered by the sacrificial emitter structure.

Claims (48)

1. A bipolar transistor, comprising:

a collector of a first conductive type;

a base layer of a second conductive type arranged above the collector;

an emitter of the first conductive type arranged above the base layer,

the collector being self-aligned to the emitter;

an emitter isolation layer laterally surrounding the emitter; and

a base link laterally physically connected to the base layer and extending lateral to the base layer,

the base link being vertically connected to a portion of the base layer and extending above the base layer, and

the base link being laterally connected to the emitter isolation layer.

2. The bipolar transistor according to claim 1 , further comprising:

a stop layer on the emitter and the base link.

3. The bipolar transistor according to claim 2 , wherein the stop layer is a SiN layer.

4. The bipolar transistor according to claim 1 , further comprising:

an emitter contact contacting the emitter, and

base contacts contacting the base link.

5. The bipolar transistor according to claim 1 , wherein the emitter has zero overlap with the base link.

6. A method comprising:

providing a collector of a first conductive type;

arranging a base layer of a second conductive type above the collector;

providing an emitter of the first conductive type above the base layer,

the collector being self-aligned with the emitter;

surrounding the emitter with an emitter isolation layer; and

laterally physically connecting a base link to the base layer,

the base link extending lateral to the base layer,

the base link being vertically connected to a portion of the base layer and extending above the base layer, and

the base link being laterally connected to the emitter isolation layer.

7. The method according to claim 6 , wherein arranging the base layer comprises epitaxially growing the base layer on a surface of a semiconductor substrate at least in an area adjacent to the collector.

8. The method according to claim 6 , further comprising:

removing a sacrificial emitter to obtain an emitter window; and

where providing the emitter includes:

providing an emitter layer of the first conductive type in the emitter window to obtain the emitter.

9. The method according to claim 8 , wherein the emitter layer is provided such that an overfill of the emitter window is achieved.

10. The method according to claim 8 , wherein the emitter layer has a minimum thickness of 60 nm.

11. The method according to claim 8 , wherein the emitter layer has a width equal to 90 nm.

12. The method according to claim 8 , wherein providing the emitter includes:

partially removing the emitter layer to obtain the emitter in the emitter window.

13. The method according to claim 8 , wherein providing the emitter includes:

partially removing the emitter layer at least up to the base link to obtain the emitter in the emitter window.

14. The method according to claim 6 , further comprising:

providing a stop layer for contact hole etch on the emitter and the base link.

15. The method according to claim 14 , wherein the stop layer is a SiN layer.

16. The method according to claim 6 , further comprising:

providing base contacts contacting the base link.

17. The method according to claim 16 , wherein the base contacts are metal.

18. The method according to claim 6 , further comprising:

providing an emitter contact contacting the emitter.

19. The method according to claim 18 , wherein the emitter contact is metal.

20. The method according to claim 6 , wherein the emitter has zero overlap with the base link.

Assignments (2)
CHANGE OF NAME Recorded Jun 12, 2024
From: INFINEON TECHNOLOGIES DRESDEN GMBH
To: INFINEON TECHNOLOGIES DRESDEN GMBH & CO. KG
Reel/Frame 067699/0648 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 10, 2018
From: MANGER, DIRK; TEGEN, STEFAN
To: INFINEON TECHNOLOGIES DRESDEN GMBH
Reel/Frame 046772/0815 →
Priority Claims (1)
DE 10 2016 207 536 · May 2, 2016 · national
Continuity (2)
Continuation 15452780 · Mar 8, 2017
Related Publication 20180323293A1 · Nov 8, 2018