Integrated circuit for simultaneous electrophysiology recording and optogenetic neural control
Various embodiments of the present technology generally relate to a single monolithic IC to perform simultaneous optogenetic neural inhibition and extracellular electrophysiological recording in-vivo. Some embodiments include a low input capacitance (e.g., 9.7 pF) amplifier particularly tailored for the use of high-impedance electrodes to conduct single neuron extracellular recording integrated with programmable high current drivers for optogenetic stimulation or inhibition on the same IC chip. Some embodiments use a noise model to guide the IC design process to obtain parameters for optimal signal-to-noise ratio. The performance of the IC chip was demonstrated on an anesthetized gerbil expressed with inhibitory optogenetic protein (Halorhodopsin). Spontaneous action potentials from the fifth nerve of the brainstem were recorded by the amplifier and were subsequently inhibited by laser illumination. As a result, various embodiments of the IC allow neuroscience research and neural engineering applications to be conducted in an entirely new direction and can potentially be used in treatments for human mental diseases in the future.
1. A device comprising:
an integrated circuit including:
a neural amplifier to receive signals from one or more optrodes measuring target neurons,
wherein the signals measuring the target neurons include measurements of action potentials or local field potentials; and
an optical driver to control an optical source to provide optogenetic stimulation or inhibition of the target neurons.
2. The device of claim 1 , wherein the neural amplifier includes multiple stages with a unity-gain buffer to maximize input impedance from the signals received via the one or more optrodes.
3. The device of claim 1 , wherein the optical driver includes a single or a multi-stage current driver that includes a first stage to provide coarse control and a second stage to provide fine control.
4. The device of claim 1 , wherein the optical driver includes a laser driver or a light emitting diode driver.
5. The device of claim 1 , further comprising a real-time spike sorting unit configured to use template matching techniques to sort the signals from the one or more optrodes based on spikes.
6. The device of claim 5 , further comprising a communication interface to receive templates created external to the integrated circuit.
7. The device of claim 1 , further comprising a real-time spike sorting unit that includes multiple template matching processes implemented in hardware on the integrated circuit that can be selectively activated by a user.
8. The device of claim 1 , wherein the multiple template matching processes include a Euclidian distance matching process and a correlational matching process.
9. A method of operating a system having an integrated circuit, the method comprising:
measuring, using one or more recording electrodes connected to the integrated circuit, neural activity of a brain of an animal or human;
processing the neural activity measured using the one or more recording electrodes to identify neuron firing;
determining, using a controller of the integrated circuit, a control action to repattern the neuron firing; and
implementing the control action in the brain of the animal or human using an optogenetic control system.
10. The method of claim 9 , further comprising identifying and sorting spikes within the neural activity measured using the one or more recording electrodes.
11. The method of claim 10 , further comprising using template classification to identify neural activity from different neurons.
12. The method of claim 11 , wherein the template classification includes multiple user-selectable options that include a Euclidian distance matching process and a correlational matching process.
13. The method of claim 9 , further comprising:
receiving, at the integrated circuit and from an external computer, a set of cluster templates to a field programmable gate array (FPGA) or an application-specific integrated circuit (ASIC);
sorting, using the FPGA or ASIC, spikes within the neural activity based on the set of cluster templates;
generating sorted neural activity based on the spikes identified locally at the integrated circuit; and
feeding, to the controller, the sorted neural activity that can be used, at least in part, in determining the control action to repattern the neuron firing.
14. The method of claim 9 , wherein implementing the control action in the brain of the animal also includes non-optical manipulation.
15. A system comprising:
a power supply;
one or more processors;
an integrated circuit;
a neural interface to receive, via one or more electrodes coupled to the integrated circuit, measurements of neural activity from a brain of an animal or human; and
a memory having stored thereon instructions that when executed by the one or more processors cause the system to:
process the measurements of the neural activity from the brain of the animal or human to identify neuron firing;
determining, using a controller of the integrated circuit, a control action to alter the neuron firing; and
transmitting the control action to an optogenetic laser system to facilitate inhibition or stimulation of neuron firing.
16. The system of claim 15 , further comprising a field programmable gate array (FPGA) or an application-specific integrated circuit (ASIC) configured to receive the measurements of the neural activity and programmed to sort spikes within the measurements of the neural activity.
17. The system of claim 15 , further comprising an optrode having the one or more electrodes that can be inserted into the brain of the human or animal to collect the measurements of the neural activity that can be transmitted to the neural interface.
18. The system of claim 15 , wherein the optogenetic laser system includes a single or multi-stage current controller to translate the control action into a desired light to facilitate the inhibition or stimulation of neuron firing.
19. The system of claim 15 , further comprising an external computer to generate a set of cluster templates.
20. The system of claim 19 , further comprising a field programmable gate array (FPGA) or an application-specific integrated circuit (ASIC) to use the set of cluster templates to classify, in real-time, spikes within the measurements of the neural activity and separate measurements from different neurons.