FinFET fabrication methods
A method and structure for doping source and drain (S/D) regions of a PMOS and/or NMOS FinFET device are provided. In some embodiments, a method includes providing a substrate including a fin extending therefrom. In some examples, the fin includes a channel region, source/drain regions disposed adjacent to and on either side of the channel region, a gate structure disposed over the channel region, and a main spacer disposed on sidewalls of the gate structure. In some embodiments, contact openings are formed to provide access to the source/drain regions, where the forming the contact openings may etch a portion of the main spacer. After forming the contact openings, a spacer deposition and etch process may be performed. In some cases, after performing the spacer deposition and etch process, a silicide layer is formed over, and in contact with, the source/drain regions.
1. A method of fabricating a semiconductor device, comprising:
providing a substrate including a fin extending therefrom, wherein the fin includes a channel region, and wherein source/drain regions are disposed adjacent to and on either side of the channel region;
forming contact openings to expose the source/drain regions;
after forming the contact openings, performing a spacer deposition and etch process; and
after performing the spacer deposition and etch process, forming a silicide layer over, and in contact with, the source/drain regions.
2. The method of claim 1 , further comprising:
after performing the spacer deposition and etch process, and before forming the silicide layer, performing a plasma doping process of the source/drain regions.
3. The method of claim 2 , wherein the plasma doping process includes a boron plasma doping of the source/drain regions.
4. The method of claim 2 , wherein the plasma doping process is a self-amorphizing plasma doping process.
5. The method of claim 2 , further comprising after performing the plasma doping process, performing a laser anneal process.
6. The method of claim 1 , further comprising:
after performing the spacer deposition and etch process, and before forming the silicide layer, performing a pre-silicide implant.
7. The method of claim 1 , further comprising:
prior to forming the contact openings, depositing an interlayer dielectric (ILD) layer; and
etching the ILD layer to form the contact openings.
8. The method of claim 1 , wherein the spacer deposition and etch process includes conformally depositing a spacer layer, and after conformally depositing the spacer layer, etching the spacer layer to provide access to the source/drain regions.
9. The method of claim 8 , wherein the spacer layer includes a silicon nitride (SiN) spacer layer.
10. The method of claim 1 , wherein the semiconductor device includes a PMOS device.
11. A method, comprising:
providing a substrate including a fin extending therefrom, wherein the fin includes a channel region, and wherein source/drain regions are disposed adjacent to and on either side of the channel region;
forming contact openings to expose the source/drain regions;
after forming the contact openings, performing an N-type dopant implant into the source/drain regions of both an N-type device region and a P-type device region simultaneously;
after performing the N-type dopant implant, masking the N-type device region and doping the source/drain regions of the P-type device region;
after doping the source/drain regions of the P-type device region, performing a spacer deposition and etch process; and
after performing the spacer deposition and etch process, forming a silicide layer over, and in contact with, the source/drain regions.
12. The method of claim 11 , wherein the doping the source/drain regions of the P-type device region further comprises:
performing a pre-amorphization implant (PAI) into the P-type device region; and
after performing the PAI, implanting a P-type dopant into the source/drain regions of the P-type device region.
13. The method of claim 11 , wherein the doping the source/drain regions of the P-type device region further comprises:
performing a boron plasma doping process of the source/drain regions of the P-type device region.
14. The method of claim 11 , wherein the N-type dopant implant includes ion implantation of indium.
15. The method of claim 11 , wherein the spacer deposition and etch process includes depositing a silicon nitride (SiN) spacer layer, and after depositing the SiN spacer layer, etching the spacer layer to provide access to the source/drain regions.
16. A method, comprising:
providing a substrate including a fin extending therefrom, wherein the fin includes a channel region, and wherein source/drain regions are disposed adjacent to and on either side of the channel region;
forming contact openings to expose the source/drain regions;
after forming the contact openings, masking an N-type region and doping the source/drain regions of a P-type region; and
after doping the source/drain regions of the P-type device region, performing a spacer deposition and etch process.
17. The method of claim 16 , further comprising:
after performing the spacer deposition and etch process, performing an N-type dopant implant into the source/drain regions of both the N-type region and the P-type region simultaneously; and
after performing the N-type dopant implant, forming a silicide layer over, and in contact with, the source/drain regions.
18. The method of claim 16 , wherein the doping the source/drain regions of the P-type region further comprises:
performing a pre-amorphization implant (PAI) into the P-type region; and
after performing the PAI, implanting a P-type dopant into the source/drain regions of the P-type region.
19. The method of claim 16 , wherein the doping the source/drain regions of the P-type region further comprises:
performing a plasma doping process of the source/drain regions of the P-type region.
20. The method of claim 17 , wherein the N-type dopant implant includes ion implantation of at least one of indium, arsenic, and phosphorous.